• TCAD Examples

mesfetex04.in : Deep Level Bulk Traps (EL2) - DC Analysis

Requires: SSuprem 4/Blaze
Minimum Versions: Atlas 5.28.1.R

This next three examples demonstrate the simulation of a MESFET structure with trap states. The example consists of several sections:

  • Formation of a MESFET structure and doping using FLASH
  • DC simulation of Id/Vgs characteristics including traps
  • - Transient simulation of gate turn off including traps
  • - Frequency domain AC simulation including traps
  • - S-parameter extraction including traps

This example will create the structure for subsequent use and perform the DC analysis.

In the process simulation section, a simple planar MESFET is formed by implantation. The initial substrate is intrinsic GaAs. A low doping level of 1.0e11 is specified. An active layer of 0.1um of n-type GaAs is deposited. A nitride hard mask is used to pattern the source and drain regions. These regions are heavily doped using a silicon implant. Finally metal deposition and patterning is performed. The electrode names and positions are then defined at the final stage of Athena.

Once in Atlas each run starts by setting the workfunction of the gate electrode. The models used in this simulation are electric field dependent mobility and SRH recombination. The lifetimes for the SRH recombination are set by the tau parameters on the MATERIAL statement. The vsat parameter sets the saturation velocity.

The trap statement is used to set the parameter of the bulk trap states. Only one state is used here but several trap statements can be used in the same run to define multiple states. The trap type must be set as donor or acceptor. The energy level of the trap is set using 'e.level'. The energy levels are referenced to the conduction or valence band edges. The sign and sigp parameters set the trapping cross sections for electrons and holes. An equivalent syntax setting lifetimes rather than cross sections is also available.

The DC simulation consists of setting the drain voltage to 0.5V and stepping the gate from zero to -1.0V. Comparing the results of this simulation with and without traps shows that a shift to a more positive threshold voltage is caused by the presence of the donor traps.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Additional Info:

Input Files
Output Results
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