A Normally-OFF Vertical Superjunction HEMT I-V Characteristics and Breakdown

ganfetex21.in : A Normally-OFF Vertical Superjunction HEMT I-V Characteristics and Breakdown

Requires: Victory Device or Atlas
Minimum Versions: Victory Device 1.14.1.R or Atlas 5.28.1.R

This example demonstrates TCAD computation of Id-Vg, Id-Vd, and Breakdown I-V characteristics of a gallium nitride (GaN) field-effect transistor (FET) called Enhancement-Mode Vertical Superjunction HEMT, with P+ Gate and P-pillar. The P+ gate region makes it a Normally-OFF (Enhancement-Mode) HEMT device.

The example is based on the following reference paper:

[1] L. Zhongda, T.P. Chow, "Design and simulation of 5-20-kV GaN enhancement-mode vertical superjunction HEMT", IEEE Trans. Electron Dev, vol.60, no.10, 2013, pp.3230-3237.

The input deck provided with this example can be run by either Victory Device or Atlas simulator, just by changing the solver name in the command go victorydevice into go atlas . It shows that both Victory Device and Atlas device simulators can be fully compatible in terms of input commands, producing same results, and allowing easy transition between Atlas and Victory Device.

This example demonstrates:

  • Construction of the Vertical GaN-FET structure using the device simulator syntax
  • Material and models parameter specification
  • Simulation of Id-Vg, Id-Vd, and Breakdown I-V characteristics
  • Display of the results in TonyPlot

The device under consideration is a Normally-OFF Vertical Superjunction AlGaN/GaN HEMT. The main concept here is that the polarization charge is calculated using the built-in models as specified by the polarization parameter on the models statement.

First, the initial solution is obtained (for zero bias), which includes also calculation of the 2D Electron Gas (2DEG) sheet density.

Then, the Id-Vg transfer characteristic is computed, for one selected Vds voltage (corresponding to Fig. 9 in the reference [1]), and then the Id-Vd output characteristics are computed, for several selected Vgs voltages (corresponding to Fig. 8 in [1]). Finally, four Breakdown I-V curves are computed for Vg = 0, 1, 2, and 3 V (corresponding to Fig. 13 in [1]).

Note that in the reference [1] a different device structure was used for the Id-Vg and Id-Vd analysis, and a different design (different dimensions and doping) for the Breakdown I-V. Therefore, the input deck has two separate sections:

- PART I: Id-Vg and Id-Vd curves computation

- PART II: Breakdown I-V curve simulation

The Part I computations are run with the standard precision of 64 bits, since increasing precision (e.g. to 80 bits) makes no visible difference in the computed I-V curves, while simulation time gets about 2X longer. However, the Breakdown I-V computations require higher precision: 80-bit for Vg > 0 V, and 128-bit for Vg close to 0 V. This is set in the very first command of the input deck, by simflags="-80" .

The families of I-V curves are plotted using the TonyPlot tool. All the computed I-V curves compare quite well with the I-V characteristics published in the reference paper [1]. You can plot similar overlaid plots yourself if you use Overlay feature in TonyPlot .

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.