Inverter using Verilog-A module

014_verilog-a_inverter : Inverter using Verilog-A module

Requires: SmartSpice & Smartview

Minimum Versions: SMARTSPICE 4.6.5.R

The 2 bit MOSFET adder input deck with .TRAN and .MEASURE analysis shows by rubberbanding the voltage source pulse parameters the sensitivity to input stimulus of simple circuit.