VCD Output

005_vcd_out : VCD Output

Minimum Required Versions: SILOS 4.12.1.C

Example 005_vcd_out, the circuit is a newspaper vending machine implemented as a Verilog gate level design. The Gateway schematics for the testbench and circuit as well as the netlist and library file are shown.

Simulate Project and Generate a VCD Output File

  • Examine the testbench source file "vend_tb_vcd.v", observe the initial block containing VCD output statements.
  • Start SILOS, open the project file "vend_tb_vcd.spjx" and click "Go" to run the simulation.
  • Open the VCD output file "vend.vcd" to examine simulation VCD output.