Analyzer - View expressions as waveforms

039_analyzer_expressions : Analyzer - View expressions as waveforms

Minimum Required Versions: SILOS 4.12.1.C

Example 039_analyzer_expressions, the circuit is a newspaper vending machine implemented as a Verilog gate level design. The Gateway schematics for the testbench and circuit as well as the netlist and the library files vend.gv and abc_100.v.

This example shows the SILOS graphical user interface feature to view an expression as a waveform in the Analyzer window.

Analyzer - View expressions as waveforms

  • Without re-simulating, you can define a search condition using any Verilog HDL expression. Scanning to the condition and viewing it as a waveform gives you quick access to important conditions of the design's operation. Searching on any Verilog HDL expression is possible because SILOS saves everything quickly and compactly to disk when simulating.
  • In this example, a search condition for when stimulus.clock and stimulus.coin[1] are both true is created.
  • Open the project gate.spjx and run the simulation.
  • Open the Analyzer window from the toolbar and show waveforms for some signals.
  • Click with the right mouse button in the Name list box in the Data Analyzer to open the context menu.
  • Select the Add Signal menu to open the Add Signal dialog box.
  • Set the scope in the Scope edit box to stimulus.
  • Enter the expression (clock && coin[1]) in the Signal edit box, and click the OK button.
  • The waveform for the expression (clock && coin[1]) will then be displayed in the Data Analyzer.
  • If you single click on the expression that you added to the Data Analyzer, pause, then press F2, you can modify the expression.
  • For example, you can change coin[1] in the expression to coin[0].