Analyzer - Source trace mode

038_analyzer_source_trace : Analyzer - Source trace mode

Minimum Required Versions: SILOS 4.12.1.C

Example 038_analyzer_source_trace the netlist for this example is a RTL behavioral description of a newspaper vending machine implemented as a Finite State Machine. Testbench netlist for this example is shown.

This example shows the SILOS graphical user interface source trace mode for behavioral code debugging in Analyzer.

Analyzer - Source trace mode for behavioral code debugging

  • Enabling Visual Debug allows behavioral code to be used with the Trace Source and the Trace Inputs capability. Trace Source displays which Verilog HDL statement caused a level on a waveform.
  • Open the project rtl.spjx and run the simulation.
  • Verify that the menu item Analyzer->Trace Source item is selected.
  • Run the simulation.
  • Open the Analyzer window from the toolbar and show some signals' waveforms.
  • Left click in the waveform window on the newspaper signal.
  • Observe that the source edit window has been positioned at an assign statement (line 105). This indicates that the state (St0) of the newspaper signal at the marker time (402ns) is a result of the assign statement being executed.