Analyzer - Input trace mode

037_analyzer_input_trace : Analyzer - Input trace mode

Minimum Required Versions: SILOS 4.12.1.C

Example 037_analyzer_input_trace, the circuit is a newspaper vending machine implemented as a Verilog gate level design. The Gateway schematics for the testbench and circuit as well as the netlist and the library files vend.gv and abc_100.v.

This example shows the SILOS graphical user interface feature using the input trace mode for gate level debugging in Analyzer.

Analyzer - Input trace mode for gate level debugging

  • Trace Inputs is the ability to trace a signal backwards through the topology to find the cause of an undesired state value.
  • In this example, the Trace Inputs feature is used to find out why the signal newspaper went from an Unknown level to a Low level at time=0.021 us.
  • Open the project gate.spjx and run the simulation.
  • Open the Analyzer window from the toolbar and show some signals' waveforms.
  • Select the "newspaper" signal and click the right mouse button to open context menus.
  • Select "Trace Inputs", then SILOS will open another waveform window which displays the VAND (stimulus.vendY.U118) waveforms. VAND is driving the output "newspaper".
  • You can continue to trace a signal backwards from VAND inputs.