Watch Window

023_watch_window : Watch Window

Minimum Required Versions: SILOS 4.12.1.C

This example demonstrates the following features of the Watch Window: Data Value Display While Stepping and Force/Set Variable Value

Example 023_watch_window circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface includes the Watch window to display variable values while stepping and to Force/Set variable values while debugging a circuit.

Watch Window Data Display While Stepping

  • Open the project "1bit_adder.spjx". Prior to running the simulation, verify the Enable Debugging button on the toolbar is depressed to enable debugging mode. Click Load/Reload Input Files button and open the Watch window.
  • Open Explorer window by click Explorer toolbar button. Select the module stimulus and drag and drop the signals a, b, c_in and c_out to the Watch window.
  • Drag and drop for same signals into Analyzer window.
  • Click step button to continue to simulation step by step and observe that the Watch window values updated as well as the Analyzer waveforms.

Force/Set Variable Value

  • Observe in the Analyzer that the signal stimulus.b is low until time 10 when it switches to high.
  • Click the Load/Reload button to reset the simulation to time 0.
  • Click the Step button twice to advance to simulation time to 5.
  • Double click on the signal stimulus.b in the Watch window to open the "Set Register Value" dialog.
  • Change the register value to 1 and click "OK".
  • Observe the value in the Watch window has been changed to "1".
  • Clock the "Go" button to finish the simulation.
  • Observe in the Analyzer that the signal stimulus.b now switches to high at time 5 when we set the register value to "1".