SILOS Supports SDF (IEEE 1497) Backannotation

002_sdf_annotation : SILOS Supports SDF (IEEE 1497) Backannotation

Minimum Required Versions: SILOS 4.12.1.C

Example 002_sdf_annotation is a drink vending machine implemented as a Verilog gate level design. Included in this example are the Gateway schematic for the circuit as well as the testbench and library files are "vcd_input.lib" and "primitives.v". The example also includes a Standard Delay Format (SDF) file that contains delay information.

Use $sdf_annotate() System Task to Read Delay Information from an SDF File

  • Start SILOS, open the project file "vcdin.spjx" and click "Go" to run the simulation.
  • The output from the simulation is written to output window.
  • Observe the message "Beginning '$sdf_annotate..." in the output window which indicates SILOS is reading SDF delay information into the simulation database.