Run/Pause simulator controls

018_run_pause : Run/Pause simulator controls

Minimum Required Versions: SILOS 4.12.1.C

Example 018_run_pause circuit is a Toggle Flip Flop defined by UDP (User Define Primitive) design. The Verilog netlist and the testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface provides the Run/Pause simulator controls.

Run/Pause Simulator Control

  • Simulate the project udp.spjx. Click the Go button on the toolbar.
  • There are two alternative ways to run the simulation. One is to select the menu item Debug->Go. and another is to just enter the "F5" function key.
  • To use the Pause function during the simulation, click the Pause button on the toolbar. You can re-start from paused time point to finish time point. You can also select the menu item Debug->Break or just enter the "F5" to pause simulation.