Module hierarchy explorer

017_module_explorer : Module hierarchy explorer

Minimum Required Versions: SILOS 4.12.1.C

This example demonstrates the following features of the Module hierarchy explorer: Module hierarchy tree display, Module port and variable list and Source code navigation options.

Example 017_module_explorer circuit is a one bit adder implemented as a Verilog gate level design. The schematic consisting of gate level primitives and the Verilog netlist generated by Gateway are shown. The testbench source file contains Verilog behavioral code to generate the input test pattern. The SILOS graphical user interface includes the module hierarchy explorer, the module hierarchy tree display, the module port and variable list, and source code navigation options.

Module hierarchy explorer

  • Simulate the project 1bit_adder.spjx. Click the "Explorer" button on the toolbar.
  • The Explorer window will be opened.

Module hierarchy tree display

  • To show the hierarchy tree, click the + (plus) icon on the left of the module "stimulus".
  • Observe that "X1: one_bit_adder" is the lower module tree.
  • Also click the + (plus) icon on the left of the module "X1: one_bit_adder", then you can see the lower modules as the gate primitive level.

Module port and variable list

  • Select one of the modules to show the list of ports and variables.
  • In this case, select the module "I1: xor21".
  • The ports and variables for this module are shown in the port and variable list window.

Source code navigation options

  • Source code navigation options allow you to show the source code file as module definition and module instance of the selected module.
  • In this example, select the module "I1: xor21".
  • Then click the right mouse button to show the context menu, and select "Go to Module Definition".
  • SILOS will automatically open the module definition file "primitive.v" and highlight "module xor21".
  • Also select "Go to Module Instance", SILOS will automatically select and highlight the module instance in the file "one_bit_adder.v".