SILOS Supports Verilog HDL (IEEE 1364)

001_verilog_hdl : SILOS Supports Verilog HDL (IEEE 1364)

Minimum Required Versions: SILOS 4.12.1.C

Example 001_verilog_hdl is a ripple counter Verilog gate level design. Included in this example are the Gateway schematics for the circuit and testbench and the Verilog library files "dff_sr.v" and "primitives.v".

Read and Simulate a Verilog HDL Netlist

  • Start SILOS, open the project file "testbench.spjx" and click "Go" to run the simulation.
  • Observe the output from the simulation is written to the SILOS output window.