OpAmp example

009_opamp : OpAmp example

Minimum Required Versions: Harmony 4.12.2.C

This example includes a SPICE top-level testbench , Verilog module to limit the simulation time to 200us and SPICE subckts to set up the simulation environment for the op-amp. The files used for this project are the SPICE netlist testopamp.in, the SPICE model file models.dat, the SPICE parameters file corners.dat, the SPICE setup file header.sp, the SPICE subckt definition file subs.sub, a Verilog testbench.v file to set the stop time testbench.v, and the connect module BiElecCon.v

Simulate the opamp circuit using Harmony.

  • Start Harmony and open the opamp.spjx project. The Harmony window title will now display <project_path>/opamp.spjx.
  • Run the simulation using the Go toolbar button.
  • Open the Explorer window by selecting View->Explorer to view the circuit hierarchy.
  • Open the Analyzer waveform viewer to view the simulation results.