SPICE top level PLL example

008_pll_spice : SPICE top level PLL example

Minimum Required Version: Harmony 4.12.2.C

This example includes a top level SPICE netlist and a Phase Detector module, Divider modules which are implemented with Verilog-HDL, SPICE netlists for modules for Charge Pump, a Low Pass Filter and final stage of Inverter, a Verilog-A VCO module, and a digital to analog (or opposite) converter connect module.

Simulate Verilog top level PLL example using Harmony.

  • Start Harmony and open the project pll_v.spjx and confirm the Harmony window title is displaying <project_path>/pll_s.spjx.
  • Check "Edit" -> "Project Properties" -> "Source Files" context dialog.
  • Run the simulation using the Go toolbar button.
  • Open the Analyzer waveform viewer "View" -> "Analyzer" to view the simulation results as this project file pll_s.spjx includes signals to be viewed without any action.