D-type Flip-Flop Verilog example

004_dff_d : D-type Flip-Flop Verilog example

Minimum Required Version: Harmony 4.12.2.C

In this D-type Flip-Flop behavioral model example we will look at the Verilog module definition and its simulation in Harmony. A Verilog-AMS testbench is used to define the digital signal sources and place an instance of the D-type Flip Flop. The Harmony mixed-signal simulator will simulate the Verilog module in the digital simulator, (SILOS code) built in to Harmony. The digital input and output signals are displayed in Harmony's design Explorer and waveform Analyzer.

Start Harmony and open the dff_d.spjx project File->Open Project for the Verilog-D DFF module example. The Harmony window title should now display the <project_path>/dff_d.spjx . To see the source files used by this project select Edit->Project Properties.

The project files are; testbench_d.v the verilog top-level testbench with instantiation of the dff_d module, and dff_d.v the DFF verilog-d module itself. Open these files, File->Open.

The testbench module uses always statements to define the clk and data signals, and instantiates DFF0 a dff_d module.

The D Flip Flop module dff_d uses a positive edge trigger on clk to set q=d.

Run the simulation, it will stop after the initialization at 0ns then hit Go again and the simulation will complete to 100ns. Turn on the Analyzer (and Explorer) to view the simulation results.

If you zoom in (left mouse click, right-mouse click, middle-mouse click) close to the transitions around 25ns you will see that the signals are digital signals with no analog type rise and fall times. The blue square wave icon in front of the signal names tells us the signals are discrete time domain signals (digital signals).