D-type Flip-Flop Verilog-AMS example using Connect Modules

011_dff_ams : D-type Flip-Flop Verilog-AMS example using Connect Modules

Requires: Harmony

Minimum Version: Harmony 4.12.2.C

In this double D-type Flip-Flop example we will look at an example of a digital DFF driving an analog DFF each of which has been instantiated in a Verilog-AMS top-level testbench. The testbench generates digital signal sources for data, clk. Harmony will need to use Connect Modules to provide the necessary A2D and D2A conversions of the various analog and digital signals in the circuit. We will look at some of the common issues raised when using Connect Modules.

Start Harmony and open the dff_ams.spjx project (File -> Open Project) for the Verilog-A DFF module example. The Harmony window title should now display the <project_path>/dff_ams.spjx . To see the source files used by this project select Edit -> Project Properties.

The project files are; main_ams.in the SPICE analog control file, testbench_ams.v the verilog top-level testbench, dff_a.vams the DFF verilog-a (ams) module itself, and dff_d.v the Verilog digital module.

Also, Harmony needs the default connect module from the installation; a copy of BiElecCon.v can be found in this example directory. The `include "disciplines.vams" definition for the inclusion of disciplines and natures is in the connect module definition. Open each of these files using the open file icon or File -> Open that will allow you easy access to see the contents of the project source files.

In the Project Properties SPICE Options window Edit -> Project Properties -> SPICE Options unclick the Use Compiled Connect Module option and also set a suitable analog sampling interval.We have chosen 2ps here, the digital parts use a timescale of 10ps and precision of 1ps. A smaller analog sampling may be more precise but may also cause more analog time-points and slower simulation than necessary.

The testbench_ams verilog module contains the usual `timescale definition. The analog ports d, clk, q for the instance DFF1 (dff_a) are defined as using the data flow voltage discipline rather than the usual electrical discipline, see the Harmony dff_a example for more details. The modules for dff_d and dff_a are instantiated using verilog-ams syntax, module_name #(parameters) instance_name(ports); DFF0 is a simple Verilog definition for a D-Type Flip Flop.

On the DFF1 instance we have specified the dir( -1) parameter making it negative edge triggered. The dff_a.vams is a purely Verilog-A analog module definition. The inputs and outputs use the analog voltage discipline while the DFF behavior is captured in the analog begin end block.

The main_ams.in file is a SPICE control file giving the length of the simulation as 100ns with a guideline timestep of 10ps.

Click on the Go toolbar button to run the simulation, it should complete in a few seconds showing your output log. But there is a problem. Harmony says that the connect modules for voltage to logic cannot be found. Although we have specified the built-in default connect modules, they do not contain modules for the connection of voltage to logic discipline, but they do contain modules for the electrical to logic discipline.

Edit your dff_a.vams file and change the voltage discipline to use electrical for the ports q, clk, d. Also, include a new parameter vdd, set to 1.8V, and make the output transition statement use vdd as the logic 1 analog signal level. Your dff_a module should like something like this.

Select Reload & Go to re-run the simulation. Now the simulation runs and the default connect modules are being used. Plot the signals on dff_d DFF0 (outd, data, clk), plot the analog signals on dff_a DFF1 d, q, and zoom in around 0-30ns. Your results should look similar to these waveforms.

Although we have simulation results we still have some issues. The analog output port q on the dff_a DFF1 component is a 1.8V switching signal while the output of the dff_a in the digital domain stays at logic level 0. The circuit looks like it is working but the vdd=1.8V supply does not seem to be used correctly. The reason is that the default Connect Modules use 5V logic but we want to use 1.8V logic.

Make a copy of the BiElecCon.v to a new file, something like BiElecCon1v8.v and change the vdd parameter setting it to 1.8. Also change the logic thresholds for V1Threshold =1.2 , V0Threshold = 0.6 so that we will have the correct voltage levels being generated by the Connect Modules.

Change your source files to include your new Connect Module and uncheck the Default Connect Module File.

Click on Reload & Go again to see the correct simulation results using your newly made 1.8V Connect Modules.

If you plot the clk signals for DFF0 (digital) and DFF1(analog) you will notice there is a delay between the clk at DFF0, DFF1 inputs when compared with the clk signal from the testbench. The Connect Modules are bi-directional so the analog ( aP ) and digital (dP) ports are connected with the feedback between them. The analog simulator cannot handle the instant transitions of the digital signals, so a pwl smoothing is applied with the smooth parameter set to 100ps by default. The smoothing causes an effective delay in the Connect Modules output at the analog port, the digital port is therefore also delayed to match this.

For the dff_a module we had 10ps transitions so it is reasonable to also set 10ps for the smoothing for the Connect Modules. Change to Smooth = 10p in your BiElecCon1v8.v Connect Module.

Reload & Go , now your results show about 7ps of delay through the Connect Module.

Connect Modules are an important part of any mixed-signal simulation. We have used the analog and digital D-Type flip flop to understand the importance of using the correct disciplines and supply voltages when working with our analog and digital behavioral models.