Verilog Function and Timing Model Generation

008_core : Verilog Function and Timing Model Generation

Minimum Required Versions: AccuCore 2.4.9.R, SmartSpice 3.16.12.R

This example explains how to use AccuCore to create a Verilog gate level netlist and Verilog gate level functional and timing simulation models from a SPICE netlist. The SPICE netlist may be either hierarchical or flat and may also contain RC parasitics. This feature is especially useful in legacy IP reverse-engineering applications.

To enable this feature specify verilog as a MODEL_TYPE in the Core_EX8.cfg file.

The Verilog simulation model output should not be confused with the Verilog gate level netlist output. The Verilog simulation model output consists of the gate level verilog function and timing simulation models that are utilized in the Verilog gate level netlist. The netlist together with the simulation models permits the running of timed gate level regression simulations in an event-driven Verilog simulator such as SILOS.

As an alternate mode, AccuCore can also be run without SPICE simulation characterization in which case only the Verilog gate level netlist and functional Verilog simulation models will be generated. This is the same capability offered in SILVACOs CatalystAD product.

Additional .cfg file commands are VERILOG_*