FAST_MODE and Other Characterization Modes

005_core : FAST_MODE and Other Characterization Modes

Minimum Required Versions: AccuCore 2.4.9.R, SmartSpice 3.16.12.R

This example explains how to use the AccuCore FAST_MODE and other characterization mode options to trade-off run-time vs. accuracy during different phases of the design and verification process. Useable results with run-times ranging from 1x to 100x (or more) sign-off mode speed can be achieved by proper application of the described methods with typical designs. Final results speed-up is design and simulation options dependent.

AccuCore FAST_MODE enables an AccuCell style method of characterization in AccuCore where the input netlist is analyzed for either existing cell hierarchy gate partitions OR automatically determined logic gate partition equivalent cells (even from a flat design input netlist). AccuCore then evaluates the range of loads that exist in the design netlist for each cell type and runs a one time characterization for each cell type to be used for timing all instances from NLDM timing table models.

In addition to FAST_MODE , AccuCore has the ability to compress timing characterization requirements so that not all instances require a full 2D NLDM timing table model to be generated when in sign-off mode. The capability is automatic and can be controlled for the level of accuracy and run-time by adjusting the parameters that control the decision engine. The following .cfg file parameters affect this processing PI_SLOPE_TABLE, SLOPE_DIFF, MIN_RISE_SLOPE, MIN_FALL_SLOPE

Another method of characterization in AccuCore is the ability to isolate portions of the design not part of paths of interest or not yet designed or the subject of a design optimization analysis and skip over their characterization. This includes early stop nodes, late start nodes, and skip over blackbox methods. The following .cfg file commands affect this processing RESTART_SCCS, SIMULATE_SCCS, SKIP_SCCS, BBOX_CAP_TABLE, BBOX_FALL_SLOPE_TABLE, BBOX_RISE_SLOPE_TABLE, BBOX_SLOPE_TABLE, RISE_SLOPE, FALL_SLOPE, RISE_SLOPE_TABLE, FALL_SLOPE_TABLE, SLOPE_TABLE, DEFAULT_SLOPE_TABLE

AccuCore also permits substituting either a constant timing value or definition of a replacement timing model for portions of the logic. The following .cfg commands affect this processing CONST_DELAY, DEFAULT_LATCH_SETUP, DEFAULT_LATCH_HOLD, DEFAULT_FF_SETUP, DEFAULT_FF_HOLD, REUSE_SCC, PATTERN_BLACKBOX, SUBCKT_BLACKBOX

NOTE PATTERN_BLACKBOX, SUBCKT_BLACKBOX will be examined in more detail in example 006_core Cell Partitioning Basics and are included here only for command categorization similarity purposes only.

Lastly, another characterization and design reuse method in AccuCore is the use of cell matching. This feature permits defining various matching tolerance parameters and a characterization results caching mechanism to allow similar cells with close design and circuit properties to share prior-characterization timing results from earlier in the run or from a prior run. This feature is most useful for ECO related incremental characterization re-runs.

AccuCore will automatically identify the changed portions of the circuit and any affected neighboring cell in a shared path and automatically limit characterization to the affected cells. The following .cfg commands affect this processing USE_MASTER_DB, LENGTH_TOL, WIDTH_TOL, AREA_TOL, PERI_TOL, CAP_TOL, CEFF_TOL, LOAD_TOL, RES_TOL, SLOPE_TOL

NOTE these last commands are included here only for command categorization similarity purposes only. These commands are examined in detail in example 013_core Incremental and Design Re-Use Methods

See the AccuCore Reference Manual for additional details regarding the use and syntax of the various parameters and commands in this example.