Large and Hierarchical Design Methods

014_core : Large and Hierarchical Design Methods

Minimum Required Versions: AccuCore 2.4.9.R, SmartSpice 3.16.12.R

This example explains methods, design flows and commands necessary to utilize AccuCore to process large blocks and hierarchically designed chips with a multiple pass, multi-pronged verification solution. Related details can also be found in example 005_core FAST_MODE and Other Characterization Modes and 013_core Incremental and Design Re-Use Methods

When dealing with large designs it is critical to ensure that the selected verification task is NOT more generally defined and broader than is necessary to achieve the true end goals of the timing verification process both at the current design/verification phase and on the whole for tapeout sign-off.

Common errors include over specification or over generalization of timing verification requirements or of the verification methodology at too early a point in the process. These types of errors in methodology are a common cause of excessive and unnecessary work when attempting to utilize AccuCore, AccuCore STA or other timing verification solutions.

Sub-dividing the verification task is often a suitable and more productive solution. Bounded approaches often result in correctly identifying problems or positively confirming a working design and can require considerably less effort then exact and complete verification down to unnecessary accuracy levels across the entire design.

Timing failure identification is often a matter of oversight of a known (or forgotten) limitation or inadvertent design error as much as it is of minute timing margin failures buried deep in the design. Even in situations where it is reasonable or practical to apply a simple and uniform verification solution on a large design, the fix for any errors found often necessitates a more limited approach to achieve the corrective action away, thereby negating any perceived advantage to the global single pass concept attempted.

Often the verification process necessitates (or is substantially aided by) the need for specific design details to effectively determine expected timing characteristics and limitations, which, on large designs, is often spread across multiple designers. Expecting a single verification engineer to absorb or be familiar with all the required details without additional external involvement with the individual designers of the various portions of the design in order to achieve the promises of a single pass verification approach are often ill-fated.

Timing verification methods that rely upon strictly non-STA methods for large designs are often filled with verification holes that easily permit simple problems that could be easily discovered by STA methods to slip by unnoticed unless significant time and effort is taken to eliminate them by custom manual vector generation.

AccuCore is ideally suited to perform a realistic and effective multiple-pass re-entrant timing verification strategy based on STA methods that provide 100% coverage for all or nearly all of the design.

Special cases were STA might not be the best solution can readily be augmented and enhanced by use of AccuCores capabilities to generate the necessary auxiliary data to permit use of gate level regression based verilog timing simulations with backannotated timing information on only the limited and necessary parts of the design that warrant this additional verification technique.

By layering the verification effort, the process of identifying and correcting timing errors is enhanced due to the increased localized focus on specific aspects of the larger design.

AccuCore permits large designs to quickly and adaptively refine the verification process to greater levels of accuracy and detail thereby permitting the maximum level of validation in the minimum period of time for initial results generation and review.

The use of the easily generated variable levels of timing detail in AccuCores hierarchically generated timing modeling system permits the wide range of verification options required with the recommended verification approach.

The combination of full path and partial critical path characterization, analysis and export simulation capabilities enable AccuCore to tailor the level of accuracy appropriate to the level of the analysis. From highly abstracted timing models to critical path based SPICE simulation accuracy.

With the nature of the verification process being a repetitive one as a result of errors found and fixed and re-verified, the ability to perform incremental and design re-use methods to a design are critical to productivity especially on large designs. Example 013_core Incremental and Design Re-Use Methods highlights in greater depth these techniques.

While most of the methods and commands specific to handling large and or hierarchical designs utilize the same ones as for smaller flat designs, the options by which some of the commands are utilized and the order of their application can necessitate a different approach when processing larger hierarchical ones. The example is this section illustrates some of these differences.

The importance of matching the AccuCore STA process in conjunction with the AccuCore characterization process cannot be understated in order to achieve the best final outcome. The two are integrally related.

Given a situation where, the entire design is standard cell based with

  • a suitable gate level verilog netlist,
  • Liberty .lib cell library timing models
  • and a suitable DSPF backannotation RC netlist,

large designs CAN be completed with ONLY utilizing AccuCore STA with its STA ONLY PrimeTime-like timing verification capabilities.

However, choosing not to consider the use of the AccuCore characterization flow to augment the timing verification process can result in less than optimal results or extended design rework efforts that additional more precise analysis might have been able to avert. Use of both the AccuCore characterization and the AccuCore STA process permits the use of critical path based SPICE export simulations.

For additional details related to the STA processing aspects and features for handling large and hierarchical designs please refer to the examples in the STA section. Specifically, 015_sta Large and Hierarchical Design STA Methods

The remainder of this example explanation focuses on the additional commands specific to AccuCore that relate predominately or exclusively to handling large and or hierarchical designs that are not discussed in other examples.

In this example the following additional .cfg file commands will be examined in more detail TOP_SPICE_SUBCKT, MAX_EXP_INPUTS, MAX_CHAR_INPUTS, MAX_LOOP_LENGTH, MAX_PATH_DEPTH, MAX_PATHS, MAX_BDD_SIZE, ONE_HOT, ONE_COLD, BDD_ORDER_SIZE, COUPLING_FACTOR, DC_PREFIX, DERIVED_CLOCKS, INST_HIER_SEP, KEEP_FLAT, MAX_DC_DEPTH, MAX_MASTER_INPUTS, NET_HIER_SEP, PORT_ORDER, RETAIN_HIER

Additionally the example makes integrated use of most of the prior methods and commands discussed in the prior examples. It is recommended that these prior examples first be completed and fully understood prior to attempting this example.

Run-times for this example will be considerably longer and require significantly more steps than the prior examples.

For additional details regarding the use of these individual commands please refer to the AccuCore Reference Manual.