SDF Timing Model Generation

010_core : SDF Timing Model Generation

Minimum Required Versions: AccuCore 2.4.9.R, SmartSpice 3.16.12.R

This example explains how to use AccuCore to create a Standard Delay Format timing file containing the backannotation delay information suitable for even-driven Verilog gate level regression timing simulation or STA.

To enable this feature specify sdf as a MODEL_TYPE in the Core_EX10.cfg file.