Chip and Block Characterization Configuration

001_core : Chip and Block Characterization Configuration

Minimum Required Versions: AccuCore 2.4.9.R, SmartSpice 3.16.12.R

This example explains the basic AccuCore design flow and modeling options for creating a Verilog netlist and custom Liberty .lib NLDM Timing model cell library for a chip or block using the embedded SmartSpice SPICE engine to perform characterization.

The input files in this example are HSPICE format netlists and models. Additional formats and external SPICE simulators are supported.

Two files control characterization and model generation:

Core_EX1.cfg

a configuration file, defines all parameters and Core_EX1.tcla simple one line Tcl script, issues the characterization execution command and defines the name of the .cfg configuration file. Any other valid .tcl scripting is permitted for additional automation control of the characterization and file management process for advanced users, but is NOT required for basic AccuCore operation.

.cfg commands MOSFET_TYPE, LIB_CMD, SUPPLY_V_HIGH, TEMP are the main method of controlling the PVT of the characterization process. When processing case-sensitive files

PRESERVE_CASE 1

MUST be the FIRST statement in the Core_EX1.cfg file which contains the details of the top level ports, conditions, file pointers and other details of the design. IN_FILE_NAME, TOP_VLOG_MODULE, INPUTS, OUTPUTS, INOUTS, CLOCKS, POWERS, GROUNDS, DO_STA are the main .cfg parameters to define basic design details.

For this example, top level ports A B C are primary inputs for which input capacitance will be characterized when the Core_EX1.cfg file includes the CALC_C_EFF 1 statement. Port CLK is a primary input clock. Port OUT is a primary output for which delay is characterized for four slopes and four loads yielding 4x4 tables with indexes defined manually by the SLOPE_TABLE, CAP_TABLE Core_EX1.cfg file statements. The design input netlist is defined in the file Core_EX1_lvs.net and specified in the Core_EX1.cfg file with the IN_FILE_NAME statement. The Verilog output netlist is specified with the TOP_VLOG_MODULE statement. The command DO_STA 0 controls running ONLY characterization and NOT STA.

Results for the identified cells in the design will be grouped together for the entire characterization run into a library level file.

A Liberty Core_EX1_sps.lib timing characterization model cell library can be generated by specifying synthesis as a MODEL_TYPE in the Core_EX1.cfg file. In the case of Non-Linear-Delay-Model (NLDM) table models, the reported values are cell rise and fall delays and edge rise and fall transition times in a 2D slope and cap load indexed table.

It should be noted that since AccuCore performs an in-place design and corner condition instance specific characterization process in its default mode, only cells at or near the primary I/O ports commonly need to have complete 2D timing table models. The majority of the internal cells typically need only a single scalar timing value. The AccuCore software will automatically determine the instances for which full or partial table results are needed. This timing compression behavior can be controlled by various options if desired for different levels of result accuracy.

Additional details regarding the generation of Liberty .lib cell library timing models is addressed in AccuCore Web Example 009_core Liberty .lib Timing Model Generation

The file Core_EX1.schlr is the Gateway schematic for the design. A plot of the schematic is included in Core_EX1.png .

To run the example type run in a write-able directory with a copy of the example files.