RS Latch Characterization

025_cell : RS Latch Characterization

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains the basics of AccuCell's characterization and modeling options for an RS latch using the embedded SmartSpice SPICE engine to perform characterization.

For some cells processing may be completely automatic. The structure of how the RS latch is constructed is the determining factor. If automatic function extraction does not produce the desired results then the use of either a .eqn equation file or a .tbl table vector file will be needed.

Additionally the use of a .func file defined with the SYNOPSYS_FUNC_FILE .cfg file command in addition to the test function with the SNPS_TEST_FUNC_FILE command for the test_cell statement and the use of the NET_FUNC .cfg file command to define the required output pin to state variable realtionship. Any additional cell or pin attributes needed can be defined with the SNPS_CELL_ATTR and SNPS_PIN_ATTR .cfg file commands.

The structure of this example is the common cross-coupled nand gate to produce the latching mechanism and has a reset and a set input and NO clock(gate) and hence asynchronous timing behavior.

This cell type is level-sensitive by nature. Variants of an RS latch can include a gate(clock) signal in addition to the reset and set pins similar to a JK flip-flop but still level-sensitive.

Back-to-back pairing of a pair of RS latches produces an RS flip-flop which is also supported, but not part of this example. Handling an RS flip-flop is done in a similar (but not exactly the same) manner as this RS latch example.