Setup/Hold Induced CLK-to-Q Degradation

021_cell : Setup/Hold Induced CLK-to-Q Degradation

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains the characterization and modeling options to address CLK-to-Q degradation effects from setup/hold timing sensitivity for a D Flip-Flop cell using the embedded SmartSpice SPICE engine to perform characterization.

Variations in CLK-to-Q cell timing can have serious implications in the design of modern VDSM chips with ultra high clock speeds and very low clock skew margins. Often cell libraries provided by third-party vendors are characterized in a generic fashion for general broad applicational use. As such the SAME cell design characterized under different conditions could have significant performance differences depending on what timing relationship the cell characterization is optimized for.

NOTE: The discussion relates to characterization conditions optimization and NOT cell design optimization.

AccuCell supports a wide range of characterization conditions for which the timing models can be optimized for. Due to Liberty .lib timing model format limitations, it is NOT possible to generate ONE timing model that will permit the modeling of Flip-Flop cells across all possible combinations of timing conditions utilizing Cell-Based timing methods. Therefore, users should be aware of these limiations and plan to characterize cells under relevent applicational conditions for optimal results.

The SETHOLD_, BISECT_, SH_*_THR and CLK_TO_Q_DELAY_FACTOR .cfg commands are have great flexibility to permit defining the various conditions under which setup/hold and CLK-to-Q timing interact to degrade or limit delay and constraint timing. While most of these commands are for use with the embedded internal SmartSpice engine, some flexibility is extended to include external SPICE simulation options as well. SILVACO has attempted to match external characterization results and methods as closely as possible to that of the embedded internal SmartSpice engine, however, an exact match is NOT possible and some result variation will exist. This is especially true when attempting to match an externally generated "golden" library with a specific set of characterization conditions for which not all required condition data is known. These differences are normal and expected and BOTH sets of results are valid and likely, the result of the afore mentioned characterization condition sensitivities. It should also be noted that ALL cell-based timing methods are subject to accuracy limitations when compared to block level timing SPICE characterization methods.

Since output clock to Q timing degrades as the setup and hold limits are neared, the option to include degradation related effects is available in AccuCell . The main .cfg commands are SETHOLD_DELABS, SETHOLD_DELREL, C_TO_Q_DELAY_FACTOR , the remaining commands exist to fine tune characterization conditions to an even greater extent.

SETHOLD_DELABS specifies the absolute delay degradation pass/fail criteria. The default is 5ps.

SETHOLD_DELREL specifies the relative delay degradation limit. The default is 10%.

NOTE: The delay is assumed to be positive and does not apply when the delay is negative.

C_TO_Q_DELAY_FACTOR specifies the factor by which the delay from the clock to output of a latch or flip-flop can be modified. The measured delay is multiplied by this factor and the result of this multiplication is added to the measured delay.

In addition to delay degradation effects, state stability can also be a factor that is affected by setup/hold sensitivity. The effect is addressed in AccuCell by the use of two .cfg file commands to control the threshold at which a state is considered to have become destablized.

SETHOLD_THRHIGH specifies the high threshold for setup and hold checks of the storage or output node. The default is 90%.

SETHOLD_THRLOW specifies the low threshold for setup and hold checks of the storage or output node. The default is 10%.

For more details on the individual SETHOLD_ .cfg commands please refer to the AccuCell Reference Manual and AccuCell User's Manual.

NOTE: Do not confuse with MAXCAP_DEGRADATION, MAX_DELAY_DEGRADATION, MAX_SLEW_DEGRADATION for maximum capacitance load calculation. In the case of an unbuffered output, these controls can ALSO be of as critical importance to timing behavior as CLK-TO-Q degradation related commands.