Characterization with Multiple Clocks

018_cell : Characterization with Multiple Clocks

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains how to perform characterization for sequential cells with more than one clock. A Flip-flop with a pair of rising and falling edge clock pins is used as an example of one such cell configuration, others are possible utilizing the same method.

Pins CLK and NCLK are dual phase clock pins which can be handled automatically when configured with proper CLOCKS statements in the cell-level .cfg file. AccuCell can also handle differential clocking, independent master-slave clocking, or both dual phase AND independent master-slave clocking(i.e. 4clks).

The CLOCKS statement not only lists the clocks in the design , but also the clock domain to which they belong and their polarity in that domain. This is achieved by the following CLOCKS syntax:



where "main" is the domain name (chosen at random) and the "!" prefix defines falling(negative) active edge polarity instead of the default rising(positive) edge polarity. As is always the case, "clocks" are NEVER defined with the INPUTS .cfg command.

In the case of master-slave clocks that are opposite polarity then the SAME method as for dual phase clocking can be used.

In the case of independent master-slave clocks then each clock gets its own clock domain. In the case of 4 phase clocking (or differential master-slave clocking) TWO clock domains are declared, EACH with a "!" negative polarity definition and hence four CLOCKS statements will be defined.

CLOCKS master mclk

CLOCKS !master mclkn

CLOCKS slave sclk

CLOCKS !slave sclkn

While the above dicussion centralizes around variation of Flip-Flops, latches AND multi-port register cells can also be handled in a similar manner.

While the storage nodes CAN be bi-directional and/or contention (overdriven) in style. The assumption is that the cell level data ports are ALL separate.

In the case of synchronizer/fifo/ring counter cells with separate input and output storage nodes, the data timing relationship of the internal node between the back-to-back registers WILL NOT be examined or be part of the final timing model and the multi-cycle nature of this cell will NOT be understood or accounted for. ONLY the boundary timing will be captured and reported, therefore it is highly recommended that for such cells that the SPICE results of ALL characterization runs be audited to ensure no metastable or psuedo-metastable events are taking place.

If any of the above conditions are NOT met then the use of AccuCore is recommended/required to examine the internal timing effects and/or create a boundary timing model for the "cell".

ONLY a limited number of the above cases can be handled automatically, with MOST requiring the use of detailed .tbl table vector files to process correctly.

Attempting to use AccuCell to characterize multi-bit wide cells (ex. 4-bit latch, counter chains) or whole FIFO/register files is NOT recommended even if the total number of pins is within tool limits. Functions with multiple internal states are NOT supported.