Verilog Simulation Models

011_cell : Verilog Simulation Models

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains the use of AccuCell's basic Verilog modeling options

A verilog simulation model udp_vlg.vcan be generated by specifying verilog as a MODEL_TYPE in the Cell_EX11.cfg file.

NOTE: Only one MODEL_TYPE statement should appear in the library level Cell_EX11.cfg file with all desired model types listed in the same statement.

Commands in the VERILOG_, VLOG_ group can also be used to control the structure and attributes of the timing checks and functional modeling representation.

Verilog modelling can be controlled indirectly by specifying it with the VERILOG_SEQUENTIAL_MODEL parameter with either the UDP, STRUCTURAL values, or directly by providing modeling details in external files with the various other VERILOG_ parameters. A structural example with merged setup and hold timing checks is provided in file structural_setuphold_vlg.v.

The Cell_EX11.cfg file VERILOG_TIMING_VALUES 1 parameter can be used to select either zero-delay "0" or actual delay "1" timing values for the generated verilog simulation model. Modeling details in external files can be utilized with the various other VERILOG_, VLOG_ commands.

For additional details please refer to the AccuCell Reference Manual and AccuCell User's Manual.