Integrated Clock Gating Cell Characterization

010_cell : Integrated Clock Gating Cell Characterization

Minimum Required Versions: AccuCell 2.6.0.R, SmartSpice 4.6.2.R

This example explains the characterization and modeling options for an Integrated Clock Gating(ICG) Cell using the embedded SmartSpice SPICE engine to perform characterization.

The AccuCell cell level .cfg file command INTERNALS specifies an internal node of the cell to which the cell gating function controls. This is a condition that is largely unique to cells of this type.

ICGs also require the use of a .tbl table file to control the vector generation process. The .tbl file can be specified by use of the cell level .cfg file command TBL_FILE_NAME.

Additionally, the Liberty .lib function statement MUST also be provided directly by use of a .func file and the cell level .cfg file command SNPS_FUNC_FILE.

Lastly, when constructing a Liberty .lib file for ICGs additional cell and pin attributes are commonly desired that can be specified with the SNPS_CELL_ATTR { clock_gating_integrated_cell latch_posedge }

SNPS_PIN_ATTR { E clock_gate_enable_pin true }

SNPS_PIN_ATTR { qn internal_node qn }

SNPS_PIN_ATTR { ECK state_function "CK * qn" }

SNPS_PIN_ATTR { ECK clock_gate_out_pin true }