Get a Head Start on Reliability Analysis Early in Your Design Cycle

Power integrity issues must be addressed as early in the design cycle as possible to avoid expensive design iterations. Layout engineers can use Silvaco's InVar Prime to estimate EM, IR and thermal conditions before physical design has been completed.

This webinar introduces the best practices for ensuring robustness and ease-of-use in performing power, EM and IR drop analysis on various types of IC designs early in the design cycle using simple and minimalistic input data. Using industry-standard input and output file formats, power integrity analysis will be demonstrated early in the design cycle as well as at the sign-off, tape-out stage. We will show how to find and fix issues that are not detectable with regular DRC/LVS checks like missing vias, isolated metal shapes, inconsistent labeling, and detour routing. InVar Prime has been used to verify a broad range of designs including processors, wired and wireless network ICs, power ICs, sensors and displays.


Presenter:

Kim Nguyen is a Senior Applications Engineer for Silvaco specializing in physical design and physical verification. Prior to joining Silvaco, Kim led physical design and tape-out teams at Intel Corporation.

He has also held key back-end applications engineering roles for various EDA companies.


Who should attend:

Physical design and physical verification engineers who work on reliability verification, EM/IR, thermal and power analysis