Accelerating TFT and FPD Design

This webinar will provide an overview of different techniques for TFT and FPD design enabled by the Silvaco EDA tool portfolio. With recent advances in display technology, circuits in display designs have enhanced their functionality and grown rapidly in size. Design and simulation of these enormous circuits are a challenge for the traditional SPICE simulators. Fast-SPICE-like simulators are far better suitable for these applications. In this webinar, we will discuss several key aspects which make these simulators popular in large circuit domain and demonstrate how to simulate a TFT-based display panel using Silvaco’s SmartSpicePro – event-driven multi-rate simulator. Following that we will discuss using the new features of Expert, Silvaco’s Layout Editor tool, for improving design productivity on FPD layout. And finally, we will discuss early voltage drop analysis techniques on large scale TFTs. InVar Prime offers an easy solution for early TFT layout analysis.

What attendees will learn:

  • Overview and demo of new FPD-related features of Expert layout editor:
    • Improved Equal Resistance Router
    • 3D RC extraction interface
    • Improved compatibility with OpenAccess
  • Key features of TFT-based display panels from the circuit simulation point of view
  • Key aspects of event-driven multi-rate circuit simulation methodology
  • Simulation performance and accuracy trade-off
  • Challenges in TFT-based display panel simulation
  • Simulation of TFT-based display panel examples
    • transient simulation
    • result accuracy comparison with SmartSpice
    • simulation performance and accuracy control
  • Key power integrity problems of layout design for TFT-based display panels
  • Transient nature of TFT displays and requirements for reliability analysis
  • Analysis performance and accuracy trade-off with layout only data
  • Challenges in TFT-based display panel voltage drop analysis
  • Examples of TFT-based display panel voltage drop analysis
  • Transient simulation performance and accuracy control


Dr. Gediminas Paulavicius is Sr. R & D Engineer at Silvaco’s Simulation Division. He is responsible for development of SmartSpicePro – Silvaco’s high-capacity, event-driven, multi-rate SPICE simulator. Before joining Silvaco in 2014, he worked in the circuit simulation, cell characterization and optimization space at Cadence and Synopsys. Dr. Paulavicius holds M. S. degrees in Electrical Engineering from Vilnius University and Wayne State University and a Ph. D. in Electrical Engineering from Wayne State University.

Andrei Karabelnikau is an Engineering Manager of Layout division at Silvaco. He has been work-ing for Silvaco for 9 years, developing and managing various IC CAD tools. Andrei holds a Master degree in Mathematics from Belarus State University.

Alex Samoylov, has over 20 years of experience in the physical implementation area including power, timing, and reliability analysis for standard cell and transistor level designs. Prior to this he was co-founder at Invarian. He has also held leadership positions in many tool development projects during his EDA career. Mr. Samoylov received his M.S. in Computer Science from Na-tional Research University of Electronic Technology, Moscow, USSR.

Who should attend:

Academics, Engineers, and Engineering Managers working on TFT, FPD and large display panel designs in the simulation space, layout or looking for solutions to improve your power integrity analysis