Active and Isolation Trench Fabrication for 100V Vertical LOCOS Power MOSFETS with VICTORY PROCESS and ATHENA

 

Introduction

Vertical LOCOS (VLOCOS) power MOSFET structures are becoming increasingly popular [1-3] for 100 V rated applications due to their high packing density, superior temperature characteristics and low on-state resistance. It has been shown that through careful design, the on-state resistance can exceed the silicon limit [4].

This article gives a review and introduction into the layout and design of such structures is given. Initially a simple 2D half-cell is considered. The basic structure is then expanded to incorporate the termination and isolation cells. In the final section the simulated process is transferred into 3D where stress effects during processing are investigated and discussed.

 

2D Device Cell Design

A simple 2D half-cell of a VLOCOS structure is shown in Figure 1. In this instance the device is formed by etching a deep trench into an N- substrate. The trench is then lined with a thermal oxide and refilled with polysilicon to form the gate.

Figure 1. Typical half-cell of a VLOCOS structure.

 

Subsequent P-, P+ and N+ implantations are made into the surface to form the P-Base channel region and the P+/N+ Source contacts.

In the upper portion of the trench only a thin oxide is grown creating a conventional MOS type gate that forms a vertical channel. In the lower portion of the trench a thick oxide is formed. This thick oxide serves to deplete the N- Drift region when the device is blocking in a similar manner to a RESURF [5] or Super-Junction [6] type structure.

The structure shown in Figure 1 was formed through mirroring an experimental process in ATHENA. The generated structure was subsequently re-meshed in DevEdit ready for electrical characterisation in ATLAS.

Although the half-cell structure shown in Figure. 1 will give valuable insight, the actual physical device is significantly larger and more complicated.

To achieve a high packing density, typically the half-cell shown in Figure 1 is mirrored. Multiple, parallel fingers or inter-digitated layouts of such full-cells are formed within a termination and an isolation ring to form a single device [7, 9]. The termination trench considered here is of a similar design to the active trench shown in Figure 1 except that the thick oxide extends the full depth of the trench. A simplified image of a multi-finger layout is shown in Figure 2.

Figure 2. Typical layout design for VLOCOS structures. Active device fingers are formed within a termination ring. A subsequent outer ring provides isolation.

 

Shown in Figure 3 is a simplified 2D cut along the A-A’ line shown in Figure 2. The active devices can be seen to the right of the figure. The termination trench, of a similar design as the active devices is shown on the left along with the isolation trench.

Large structures, such as that shown in Figure 3 can be made quite easily using ATHENA and DevEdit. In this instance a single active device half-cell along with a termination cell and an isolation trench cell were formed in ATHENA. The active half-cell was repeatedly imported into DevEdit where it was stitched to the preceding active half-cell along with the termination and isolation trench cells. Such a methodology negates the need to run complex, CPU intensive, large area processes in ATHENA.

The half-device segment shown in Figure 3 was then re-meshed in DevEdit for electro-thermal simulations in ATLAS. Incorporating a high number of active device cells and the termination and isolation structures enables the designer a more accurate view of the devices electro-thermal operation as self heating across the entire device as well as the increase in drain resistance due to the N+ Drain Sinker and buried layer can, amongst other things be taken into account more accurately.

Figure 3 Simplified test cell along the A-A’ cutline shown in Figure 2 including both the termination and isolation trenches.

So far we have only considered simplified 2D structures. Such structures may give us an appreciation for the physics of operation of the device but from reviewing the simplified layout shown in Figure 2 it is clear the design is inherently 3D. The end design of the active fingers and the corners of the termination ring are critical and must be carefully considered for two reasons. Firstly electric field crowding can occur at the corners degrading the breakdown voltage. Secondly, during the growth of the thick vertical LOCOS high stress effects can occur.

When considering thermal oxide growth, as is the technique used to line the trenches, typically on a concave surface (considered here to be the silicon substrate) the stress tends to be compressive (such as at the bottom of the trenches). Conversely, on a convex surface (as is found in the transition between thick and thin oxides) the stress in the silicon tends to become tensile. In the basic 2D device shown in Figures 2 and 3 it is clear that we already have the potential for a complex stress inter-relationship between concave and convex corners.

If we now consider the physical 3D device, it is clear that the complexity of the problem is significantly magnified. We must now also consider the curvature at the ends of the active fingers and the internal and external corners of the termination trenches.

To fully understand the inter-relationship generated between stress at the various internal and external corner regions full 3D process simulations must be undertaken on the VLOCOS concept.

 

3D Process Simulations

Both the termination and active cell were treated independently in VICTORY PROCESS, Silvaco’s 3D process simulator. The process developed in ATHENA that was aligned to an experimental process was reproduced in VICTORY PROCESS. The transition from an ATHENA deck to a VICTORY PROCESS deck is quite an elementary task due to the similarities in the syntax.

 

Stress in Silicon

Stress can both enhance and degrade device performance. Under high compressive stress, dislocations can form in the silicon lattice degrading device mobility [8]. Conversely, tensile stress can also be used to enhance device performance.

Virtually every process step can introduce stress into the silicon wafer. These include, but are not limited to: thermal processing, film edges, embedded structural elements, dislocations in doped lattices, epitaxy and non-planer thermal oxidation. This latter effect, which is found during the formation of the active trenches discussed in the previous sections, is the sole focus of the following study.

Under thermal oxide growth conditions stress occurs due to two reasons: I) thermal mismatch between the oxide and the silicon substrate, and II) from the actual growth and consumption of the silicon by the growing oxide. This is referred to as “intrinsic stress” [10].

In a typical trench process, not only will the thermal oxidation of the trench cause stress in the substrate but two other factors can also introduce stress: I) the thermal mismatch between the substrate, the grown film and the re-fill material, and II) the intrinsic stress of the re-fill material [10].

In the following 3D trench process stress study we shall just be considering the thermal oxidation of the trench and the stress generated in the oxide.

Oxidation

In VICTORY PROCESS, fast geometrical processing steps that perfectly mimic optimised etching and deposition steps can be applied to quickly arrive at an input structure for the critical processing steps. These critical (oxidation) steps have been analysed through a comprehensive physical process step simulation.

The critical process step that is considered here is the thermal growth of the trench oxide liner. For the analysis of the VLOCOS process, the viscous material flow model has been applied. It is governed by the following equation:

Stress tensor profile of oxidation induced stress

Viscosity of all materials

Deformation velocity field

This model gives the full oxidation induced stress profile in all materials that are deformed as a consequence of the oxidation of silicon.

The transport of the oxygen to the silicon interface has been model using a linear diffusive transport model:

The combination of both models is referred to as the “linear-viscous” model in VICTORY PROCESS.

This set of equations is solved on a hierarchical Cartesian mesh with floating interface points. In order to solve the oxidation equations on Cartesian meshes it is also necessary to have regular mesh points within all material layers. This has the potential to require very fine meshes. Therefore the physical 3D solution is coupled with empirical 1D solutions within very thin planar regions to keep the number of mesh points reasonably small.

There is one limitation that we must recognise when using the linear viscous model, namely that the oxidation rate is not stress mediated. Therefore in high stress regions such as at the trench corners it is possible that there will be some minor differences in the thickness of the simulated oxide when compared against experimental results.

 

The 3D VLOCOS Simulation Analysis

Three different layouts were considered in this study both for the termination trench and the active device trench. Due to the similarity in design between the termination trench and the active device trench, the active device trench is used as the sole focus in the following discussion.
In all three of the layout designs considered, the initial trench width was set at 1.0 um, the thin MOS oxide extends 1.5um into the silicon, and the thick oxide liner extends a further 5um. Both the thin and thick oxide liners were thermally grown. The thin oxide is 20nm thick whilst the thick oxide is 500nm.

The first layout design is shown in Figure 4a. This is a simple ninety-degree corner design. The nitride layer used to protect the thin MOS channel oxide during the growth of the thick oxide has been left in place. To highlight the similarities between the active device design and the termination cell design, a termination cell of the same corner layout is shown in Figure 4b.

Figure 4a. Ninety-degree active device corner post thick thermal oxide growth.

 

Figure 4b. Ninety-degree termination corner.

 

Shown in Figure 5 is the second design. In this design, a forty-five degree cut has been taken across the corner. In the third and final design that is shown in Figure 6, a double cut is taken across the corner.

Figure 5. Alternative corner design: forty five-degree cut corner.

 

Figure 6. Alternative corner design: Double cut corner.

 

It is quite an elementary task in VICTORY PROCESS to vary the layout design in the manner presented here. Areas can be masked off either through using an arbitrarily defined geometry within the deck, or a mask in .lay or GDSII format may be imported into the process flow.

Due to the tighter angle of the ninety-degree design it is considered that stress effects will be more pronounced in this design and so it is subsequently the focus of the following discussion.

Shown in Figure 7 are the stress contours in the oxide trench liner for the ninety-degree corner layout design. The silicon substrate has been hidden to enable full viewing of the internal and external trench corner area.

Figure 7. Stress contours in the oxide of the ninety-degree corner trench. Highlighting the critical compressive and tensile regions.

It is clear that a high level of compressive stress is generated during the thermal oxidation of the trench in three key areas: the trench oxide bottom, the shoulder of the thick oxide below the thin MOS channel oxide, and on the external corner of the oxide trench. It is considered in [10] that for the case of stresses at film edges and in trenches (as is the case in this study) where stress singularities occur, it is impossible to state a level of compressive stress at which mobility degrading dislocations or crack propagation would occur. Although it was shown in [9], where similar structures are studied that at compressive stress levels greater than 0.5 GPa dislocations can be observed experimentally through the use of SEM on prepared samples.

Two key areas of tensile stress can also be observed. Firstly on the internal corner of the trench oxide, and secondly on the transition between thick and thin oxides.

The formation of high tensile stress in this region is in agreement with that reported experimentally in [9]. The authors also demonstrated that the high tensile stress formed in this area enabled an enhancement in device characteristics.

 

Conclusions:

ATHENA was initially used to import an experimental VLOCOS process so as to gain a basic physical understanding of the device. The basic structure was then enlarged in DevEdit to include further active cells and termination and isolation cells for subsequent electro-thermal simulations.

The ATHENA process was transferred into VICTORY PROCESS where 3D layout effects were considered.
The stress formed during the thermal oxidation of the trench highlights the importance of considered design. The location of the stress peaks was found to be in agreement with experiments reported in the literature.

 

Acknowledgements:

This work was supported by the UK Government, Department For Trade and Industry (DTI) Technology Program, ‘SSPICC’, TP/3/DSM/6/I/16949

We also wish to acknowledge Dr M. R. Sweet and Prof S. N. E. Madathil at the Electrical Machines and Drives Research Group, University of Sheffield, Sheffield, England

 

References:

  1. Y.C. Liang, K..P. Gan and G.S. Samudra, “Oxide bypassed VDMOS an alternative to super-junction high voltage MOS power devices”, IEEE EDL, 22, pp.407-409 (2001).
  2. M. Kodoma, E. Hayashi, Y. Nishibe and T. Uessugi, “Temperature characteristics of a new 100V rated power MOSFET, VLMOS”, International Symposium on Power Semiconductor Devices 2004, pp.463-466.
  3. P. Moens, F. Bauwens, B. Desoete, J. Baele, K. Vershinin, H. Ziad, E.M. Shankara Narayanan and M. Tack, “Record-low on-Resistance for 0.35 μm based integrated XtreMOS Transistors”, International Symposium on Power Semiconductor Devices 2007, pp.57-60.
  4. P. Moens, F. Bauwens, J. Baele, K. Vershinin, E. De Backer, E.M. Sankara Narayanan, M. Tack, “XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit” International Electron Devices Meeting, 2006. 11-13 Dec. 2006.
  5. J. Appels and H. Vaes, “HV thin layer devices (RESURF devices)”, International Electron Devices Meeting Technical. Digest, 1979, pp. 238-241.
  6. T. Fujihira, “Theory of Semiconductor Superjunction Devices”, Japanese. Journal of Applied Physics, 36, 1997 pp. 6254-6262.
  7. R. Lerner, U. Eckoldt, A. Hoelke, A. Nevin, G. Stoll, “Optimized deep trench isolation for high voltage smart power process”, International Symposium on Power Semiconductor Devices and ICs, 2005. 23-26 May 2005 pp135 - 138.
  8. I. De Wolf, “Raman Spectroscopy: About Chips and Stress”, Spectroscopy Europe, 15, 2003, p6-13.
  9. P. Moens, J. Roig, J. Meersman, J. Baele, B. Desoete, M. Tack, I. De Wolf, “μ-Raman Validated Stress-Enhanced Mobility in XtreMOS Transistors” International Symposium on Power Semiconductor Devices and IC’s, 2008. 18-22 May 2008, pp. 84 – 87.
  10. S. M. Hu “Stress-related Problems in Silicon technology” J. Appl. Phys. 70 (6), Sept. 1991 pp. 53 - 80.

 

Download PDF Version of this Article