TCAD Modeling and Data of NOR Nanocrystal Memories

S. Jacob (1, 2), L. Perniola(1), P. Scheiblin(1), B. De Salvo(1), G. Lecarval(1), E. Jalaguier(1), G. Festes(2), R. Coppard(2), F. Boulanger(1), S. Deleonibus(1)
(1) CEA-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France, stephanie.jacob@cea.fr(2) ATMEL Rousset, Zone industrielle, 13790 Rousset, France

 

Introduction

It is widely believed that the scaling of standard Flash devices will face in a near future several limitations, due to the high voltage requirement of the program/erase and the stringent charge storage requirement of the dielectrics [1]. Among the possible solutions to push further the scaling limits of standard technologies, Si nanocrystal (Si-NC) memories are one of the most promising. It has been shown that thanks to the discrete nature of Si-NC, thinner tunnel oxide can be used (allowing lower operating voltages), without compromising the reliability [2, 3]. Indeed, a first understanding of the Si-NC memory behaviour can be achieved through simplified/semianalytical models [4, 5, 6]. Nevertheless, these approaches are not enough accurate to allow the optimization of the technological parameters, especially for NOR cells, written by channel hot electron (CHE) injection. To this aim, more complex numerical models, which take into account twodimensional (2D) or even three-dimensional (3D) effects, should be used.

In this work, we present TCAD simulations of NOR NC memories performed with commercial tools, which allow for a good understanding of the impact of the localized charge on both electrostatics and dynamics of the cell. Correlations with experimental results will be also presented.

 

Devices and Simulation Tools

Devices tested in this work are NMOS memory cells with a layer of LPCVD (Low Pressure Chemical Vapor Deposition) Silicon nanocrystals acting as floating gates. The mean diameter of nanocrystals is about 5 nm and the density is 1E12 dots/cm2. The tunnel and top oxide dielectrics are thermal SiO2 and HTO (High Temperature Oxide) with a thickness of 4 nm and 10 nm, respectively. The gate length of the cell is 0.23 µm and the width is 0.16 µm (corresponding to the ATMEL 0.13µm NOR Flash technology node).

Two- and three-dimensional simulations have been performed with commercial TCAD tools [7]. Structures fed to the device simulator, including doping profiles, were obtained from 2D process simulations (2D profiles were then extruded in the third dimension for 3D simulations). In the simulated devices, nanocrystals are approximated as metallic cubes with 5 nm edge and a density of 1E12 dots/cm2.

 

Electrostatic Simulations

A. Comparison between a 3D “random-distributed” NC memory cell and a 2D “ordered” NC memory cell

A three-dimensional structure, where the embedded nanocrystals are randomly distributed (both along the device length and width), was firstly simulated (see Fig.1). Indeed, this structure resembles the actual device, but 3D simulations imply high computational burdens. To bypass this limit, a 2D NC device (see Fig.2), where the embedded nanocrystals are ordered (i.e. equally spaced along the cell length and extending like rod structures along the device width) was also simulated. Due to the ordered nanocrystal configuration, in 2D uniformly charged devices, the trapped electrons give rise to a wave-like modulation of the surface potential along the device length, while creating a uniform potential barrier over the device width. An agreement between electrical results of the 2D and 3D structures should be quantitatively demonstrated.

Figure 1. View of the 3D simulated structure with randomly distributed nanocrystals.

 

Figure 2. View of the 2D simulated structure with ordered nanocrystals.

 

 

Fig.3 shows a comparison between the transfer characteristics (in the virgin and written states) of these two structures. In the written state, the nanocrystals located in a region extending about 80nm from the drain junction on the active channel have been uniformly charged (with 10 electrons per dot). This situation corresponds to memory cells operating in NOR configuration, written by channel hot electrons. Note that, in order to have the same surface charge density in 2D and 3D simulations, the number of electrons trapped in 2D nanocrystals (which, as already said, extend like rod structures all along the device width) is normalized, by means of a multiplicative factor which takes into account the real nanocrystal coverage ratio along the device width [4]. From Fig. 3, it clearly appears that the 2D and 3D structures have similar behaviours. Based on these results and due to the significant improvement in computational time for 2D structures with respect to the 3D ones, the former has been the preferred choice for the next simulations.

Figure 3. Simulated transfer characteristics of the 3D and 2D structures, in the virgin and written states. Reading Vds = 0.1V.

 

B. Influence of the charged region length on the memory programming window

Electrical simulations of memory devices with different uniformly charged region lengths, extending from the drain junction (i.e. different numbers of uniformly charged NCs), and different numbers of electrons per dot, were performed (see Fig.4). It clearly appears that the memory programming window (Vt) saturates well before the charged region covers the entire memory channel. For a 0.23 µm cell length, a charged region extending from the drain junction toward the channel of about 150 nm makes the Vt saturate to a value which linearly depends on the number of trapped electrons per dot (linked to the writing bias conditions and to the dot size [8]). Indeed, this result suggests that, to achieve high memory Vt, the HE writing conditions should take care of optimizing the current injection peak in a region close to the drain junction, more than trying to extend the electron injection all over the channel.

Figure 4. Simulated programming window as a function of the charged area length (extending from the drain junction). Reading Vds = 1V.

 

 

Hot-Electron Programming Simulations and Experimental Data

The 2D device simulations were performed with ATLAS TCAD commercial tool [7]. Fig. 5 illustrates the comparison of simulated programming injection currents of a NC cell under hot electron writing for different transport models: energy balance transport model [9, 10] and drift-diffusion model [11]. In both cases, for the hot electron injection in the dots, the lucky electron model [12] was used. When the lucky electron model is associated with the energy balance model, an effective electric field depending on the carrier temperature is calculated. In agreement with the literature [13], we observe that the drift-diffusion model fails to predict the injection current in the channel region. In particular, the simulated program efficiencies based on the drift-diffusion model resulted much lower than the experimental ones (especially at low-medium voltages), essentially due to the fact that the injected charges are confined in NCs located very close/above the drain junction, and so not affecting the device threshold voltage. Note that, this behaviour is much less critical in the case of standard Flash memories, where the injected charges are immediately distributed in the continuous floating gate whatever the injection point position.

Figure 5. Comparison of 2D simulated nanocrystal devices under hot electron programming (Vdstress=4V, Vgstress=8V, tstress=10µs, Vbulk=0V, Vs=0V) with different transport models in the channel (drift diffusion and energy balance). Up: Electric fields in the simulated device. Down: Left - Potential cuts in the charged dots (1); Right – Injection current density distributions (at 1nm from the Si/SiO2 interface (2)).

 

A good agreement between simulations and experimental data was obtained by using the energy balance transport model [9, 10] plus the lucky electron model [12] for the electron injection in the dots. Figs. 6 and 7 show the simulated transfer characteristics of written NC memory cells, parameterized as a function of the stressing time (tstress) and of the stressing gate voltage (Vgstress), respectively. In the Insets of the same figures, the simulated programming windows are compared with corresponding experimental results obtained on NC cells. As we can observe in Fig.8, the lateral location of the largest charged NC remains the same for different Vg stresses. On the other hand, similar analyses with respect to the stressing time (see Fig.9) show that the charges which are progressively trapped in the NCs modify the local barrier and shift the current injection point toward the channel. Fig.9 also reports a potential cut among NCs, showing that the stressing time which corresponds to charged NC located far from the drain junction also corresponds to the higher programming window (see Fig.7).

Figure 6: Simulated Id-Vg of the 2D device, virgin and written by HEI with different writing gate voltages (tstress=10µs, Vdstress=5V, Vbulk=0V, Vs=0V). Device is read at Vds=0.5V. Inset: Comparison of simulated programming windows ( Vt @ Id=10-7A) and corresponding experimental ones.

 

Figure 7: Simulated Id-Vg of the 2D device, virgin and written by HEI with different writing times (Vdstress=5V, Vgstress=8V, Vbulk=0V, Vs=0V). Device is read at Vds= 0.5V. Inset: Comparison of simulated programming windows ( Vt @ Id=10-7A) and corresponding experimental ones.

 

Figure 8. Up : Electric fields in 2D devices corresponding to Fig.6 (i.e. different writing gate voltages, Vdstress=5V, tstress=10µs, Vbulk=0V, Vs=0V). Down: Left - Potential cuts in the dots (1); Right – Injection current density distributions (at 1nm from the Si/SiO2 interface(2)).

 

Figure 9. Up : Electric fields in 2D devices corresponding to Fig.7 (i.e. different writing times, Vdstress=5V, Vgstress=8V, Vbulk=0V, Vs=0V). Down: Left – Potential cuts in the dots (1); Right – Injection current density distributions (at 1nm from the Si/SiO2 interface (2)).

 

 

 

Conclusion

Two- and three-dimensional TCAD simulations of NOR nanocrystal memories have been presented. The electrostatic and dynamic behaviours of the cell have been studied and compared to experimental data. The key role of the position of the trapped charges along the channel length on the threshold voltage shift has been put in evidence. Indeed, this result is critical for NOR discrete-trap memories, where the HE injection is essentially aligned with the drain junction.

 

References

  1. G. Atwood, IEEE Trans. on Dev. Mat. and Rel., 4, 301, 2004.
  2. B. De Salvo et al., IEEE Trans. Device Mater. Reliability, 4, 377, 2004.
  3. R.Muralidhar et al., Techn. Dig. of IEDM, 601, 2003.
  4. B. De Salvo et al., IEEE Trans. on El. Dev., 48, 8, 1789, 2001.
  5. A.Campera et al., Solid State Electronics, 49, 1745, 2005.
  6. C.Compagnoni et al., IEEE Trans. on El. Dev., 52, 4, 569, 2005.
  7. http://www.silvaco.com
  8. M. J. Gordon et al., Phys. Rev. B 72, 165420, 2005.
  9. R.Stratton, Phys. Rev., 126, 6 (1962): 2002.
  10. R.Stratton, “Semiconductor Current-Flow Equations (Diffusion and Degeneracy)”, IEEE Trans. Electron Devices Vol. 19, No. 12 (1972):1288-1292.
  11. S.Selberherr, Analysis and Simulation of Semiconductor Devices. Wien, New York: Springer-Verlag, 1984.
  12. Tam, S et al Luckyelectron Model of Channel Hot-electron Injection in MOSFET’s, IEEE Trans. El. Dev. 31, 9, 1984.
  13. R. Hagenback et al., Journ. of Computational Electronics 3:239 242, 2004.

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