Evaluating of the Avalanche Failure of Power MOSFETs using ATLAS

Introduction

Power MOSFETs are widely used with an inductive load for S/W power supplies, DC-DC converters, and so on. But due to high frequency operation, the surge voltage applied to the MOSFETs at turn-off depends on the inductance and parasitic inductance in the circuit. For some operation modes, the pulse width for the turn-on or off will be very short, and the device fails due to the short surge period.

In this article, the device simulator ATLAS was used to to predict the maximum inductive loads and find out the failure current due to the device intrinsic temperature.

 

Single Pulse Unclamped Inductive Switching

Figure 1 shows that the single pulse unclamped inductive switching (UIS) test circuit for avalanche testing. Figure 2 shows the traditional operation waveform (avalanche operation waveform)[1].

Figure 1. Single Pulse Unclamped Inductive Switching (UIS) Test Circuit.

 

Figure 2. Operation Waveform (Avalanche Operation Waveform).

 

The avalance current (IAV) depends on both the inductance value and the direction of the on time (PW). Therefore, to get a high IAV a small inductance or a long on time should be chosen.

From the circuit shown in Figure 1, the single pulse avalanche energy (EAV) can be calculated:

(1)

The measured energy value depends on the avalanche breakdown voltage, VDSS, which tends to vary during the discharge period due to the device temperature increase. Also for low VDSS-VDD, there is limited use of this circuit because it introduces a high-test error. Here the most important value is BVDSS, which depends on the device temperature. So the effects of self-heatin should be also considered to predict the device operation and avalanche failure.

 

Avalanche Failure Mode Analysis

I. Active Mode (Parasitic Bipolar Effect)
Most semiconductor devices contain parasitic components intrinsic to the physical design of the device. In power MOSFETs, these components include capacitors due to displaced charge in the junction between p and n regions, resistors associated with material resistivity, a body diode formed where the p+ body diffusion is made onto the n- epilayer, and an NPN sequence (BJT) formed where the n+ source contact is diffused[2].

Figure 3a shows a U-Groove gate region design, and Figure 3b shows the complete circuit component model. This structure has already been considered for gate charging characteristics.[3]

Figure 3a. Typical Power UMOSFET Structure.

 

Figure 3b. Power MOSFET Circuit Models.

 

In avalanche, the p-n junction acting as a diode no longer blocks voltage. With higher applied voltage a critical field is reached where impact ionization tends to infinity and carrier concentration increases due to avalanche multiplication.

The electric field inside of the device is most intense at the point where the junction bends. This strong electric field causes maximum current flow in close proximity to the parasitic BJT. The power dissipation increases temperature, thus increasing Rb, since silicon resistivity increases with temperature. When the voltage drop is sufficient to forward bias the parasitic BJT, it will turn on with potentially catastrophic results, as control of the switch is lost. But in practice the failure is passive mode due to the thermal effect under UIS conditions (Figure 1 and Figure 2).

 

II. Passive Mode (Thermal Effect)

During unclamped inductive switching as the MOSFET is subjected to increasing energy, the internal chip temperature rises dramatically as in Equations 2 and 3.

(2)

 

(3)

where IAV and EAV are the avalanche current and single pulse avalanche energy respectively. But this approximate calculation has a large error when predicting the internal device temperature.

ATLAS with self-heating and MixedMode can simulate the exact the device temperature dependance on the channel doping profile and parasitic BJT as well as the avalanche breakdown voltage due to the device temperature.

 

Simulation Results and Discussion

Figure 4 shows the traditional single pulse UIS wave form. This UIS condition does not consider the effects of self-heating and the device temperature is constant at the room temperature.

Figure 4. UIS without self-heating effects.

 

The avalanche operation time can be obtained but it is not possible to tell if this circuit is under safe operation conditions or not. So if the self-heating effects are considered with thermal resistance, then the effects of that device capability on the UIS condition can be found. Figure 5 shows that the test power device has a breakdown voltage of 58V at room temperature[4].

Figure 5. Power MOSFET breakdown voltage is (58V).

 

Under UIS circuit conditions, Vbs/3~=20 V was chosen. To predict the safe operation range, the inductive load (L) and the avalanche (IAV) current was varied. The inductive load was chosen as 0.1mH, 1mH, 10mH. For 0.1mH and 1mH the avalanche current was simulated from 10A to 50A with a 10A step. For 10mH, the avalanche current was simulated from 5A to 10A with a 1A step.

For safe device operation under UIS, the maximum device temperature must be under 608K(335C). For power MOSFETs, at this temperature, current increased rapidly, forming a localized hot spot that quickly becomes a destructive mesoplasama.

Figure 6 and Figure 7 show the switching avalanche waveform. Figure 6 shows that the maximum device temperature is lower than the device intrinsic temperature, (335C) while Figure 7 shows that the maximum device temperature is higher than 335C.

Figure 6. Lower than the 608K of the device temperature condition.

 

Figure 7. Higher than the 608K of the device temperature condition.

 

Figure 8, can be used to find the device safe operation range under UIS conditions. In this plot, the blue line is from the simulated data, X is avalanche failure condition, O is avalanche safe condition. Depending on the inductive load and avalanche current the predicted safe operation range is close to the measured data(red line).

 

Figure 8. Plots of the Device Safe Operation and Avalanche Failure on UIS condition at ambient temperature 25C.

 

Conclusion

This article shows the capability of ATLAS to predict the avalanche failure of the power devices under the Unclamped Inductive Switching (UIS) conditions. During single pulse UIS, the device temperature is higher, and under some conditions, the device temperature is can exceed the intrinsic temperature (335C). ATLAS can be used to predict the safe operation range.

 

Reference

  1. K. Ghandhi, Semiconductor Power Devices (Wiley-Interscience: New York, 1977)
  2. A. Narazaki, K. Takano, K. Oku, H. Hamachi and T. Minato, “A Marvelous Low on-resistance 20V rated Self Alignedment Trench MOSFET(SAT-MOS) in a 0.35um LSI design rule with both high forward blocking voltage yield and large current capability”, ISPSD’04. 7-1, p.393-396
  3. Simulation Standard p.4, August 2005, Silvaco Internatinal
  4. Chenming Hu and MinHwa Chi, “Second Breakdown of Vertical Power MOSFETs”, IEEE ED-29, 1287-93(Aug. 1988)

 

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