Capacitance Coupling Calculation of IPS mode TFT-LCD Using CLEVER

 

Introduction

The increasing demand of the TFT-LCD industry has lead to a rapid growth in display size and resolution. The higher cell packing density results in a narrowing viewing angle and image degradation due to electrical coupling between the data bus lines and display electrodes. This “crosstalk” therefore becomes a serious limitation. The in-plane switching(IPS) mode has been used as an excellent technology solution for realizing extremely wide viewing angles. The IPS-mode TFT-LCD has however a drawback of lower aperture ratio than the twist nematic(TN)-mode TFT-LCD when the pixel size is larger than about 140 dots per inch(1)

 

Figure 1. Conventional IPS mode TFT-LCD vertical structure.

 

Figure 2. CLEVER structure – see the taperd shape of common electrode.

 

If the electrode structure of the IPS implementation is not properly designed, it will result in a small aperture ratio and a visible crosstalk distribution.

It is well known that the crosstalk caused by parasitic capacitive coupling between driving electrodes and data-bus lines could result in image degradation

The crosstalk can be reduced by a thick dielectric film such as SiNx between the data-bus line and the common electode of the IPS structure.

It is reported that a low dielectric constant organic passivation film is a good candidate to reduce crosstalk rather than the same thickness of an inorganic layer considering manufacturing cost. A major effort to reduce the crosstalk of the IPS mode TFT-LCD is to optimize the electrode configuration to shield the pixel electrodes and the display area from the varying data-line voltages

As a result, the IPS mode is more sensitive to process variations not just the LC itself. So variation in array process, electrode width, height and surface topology must be accurately token into account.

Consequently, the optimum thickness of the organic layer or inorganic insulator layer is very important for both the cost and performance of the LCD-TFT display.

In this article we will show that CLEVER gives a good agreement with measuremt for TFT-LCD pixel structure and have the capability to study crosstalk effects of IPS-mode TFT-LCD.

 

CLEVER for Flat-Pannel Display

CLEVER has been successfully demonstrated very accrurately to extract parasitics even at very deep-submicron era. CLEVER vconsider aspect ratio which is the mesh quality of active rand pixel region. Also gate metal pattern with angle and undercut can be simulated. So accurate shape of metal and film topology using advanced CLEVER3D process simulation is indispensable to predict accurate IPS TF-LCD parasitic capacitance and so crosstalk. Table 1 show good agreement with measurement of different common-pixel electrode structures.

meas(total)(fF)
CLEVER(Clc/Cdc/Clc+Cdc)
Ref
1
2
99.6
93.46
91.25
51.0
53.4
104.4
41.2
52.6
93.8
36.5
54.3
90.8

Table 1. Common-Pixel & Common-Data Capacitance with different Common-Pixel Electrode Spacing(accuracy=5%)

*liquid crystal permittivity = 12.1

Ref/1/2: Pixel-Common space is increasing order.

 

Figure 3. Equivalent circuit of pixel.

 

 

Couping Capacitance Calculation of IPS Mode TFT-LCD Using CLEVER

Coupling voltage of the pixel electrode dVp is defined as,

(1)

Compared to TFT-TNs, the denominator of eq.(1) is small because all the electrodes are arranged on the same side of the substrate. Therefore in order to suppress Vp in the IPS mode TFT-LCD, Cpd1 and Cpd2 been to be smaller than those of the TN mode TFT-LCD.

Capatitive coupling ratio, CCR is a good approximation representing the degree of crosstalk.

(2)

 

Clc: liquid crystal capacitance
Cpd1/Cpd2: coupling capacitance from the adjacent data line and the data-line to the pixel electrode
Cpg1/Cpg2: coupling capacitance from the adjacent gate line and gate line to pixel electrode
Cpo: coupling capacitance from the pixel to common electrode in the array substrate
Cgs: TFT gat-to-source parasitic overlap capacitance
Cst: storage capacitance

With respect to the voltage dependent Clc, we can consider the permittivity of LC material, contact when constant field is applied.

The data-pixel capacitance and data-common capacitance of various IPS structrure was simulated using CLEVER(4).

Figure 4. Coupling cap. of IPS structure.

 

RC Delay

From extracted parasitics netlist, we can simulate the RC delay effect across data line directly using SmartSpice simulation. In this simulation, only one pixel was simulated.

Figure 5. Example spice input file to pixel simulation.

 

M1 drain gate ito nTFT w=49u l=38.5714u
As=1274p Ad=2439p Ps=150u Pd=610u
Nrs=0.142857 Nrd=0 geo=0
C1 substrate gate 7.0162449e-14
C2 substrate drain 1.815544e-14
C3 substrate data 2.0479665e-14
C4 substrate ito 1.4275399e-13
C5 gate drain 1.169502e-13
C6 gate data 4.7088442e-14
C7 gate ito 4.6344247e-13
C8 drain ito 4.1971866e-15
C9 data ito 7.8982418e-15

lib “tft.lib” ntft
vg gate 0 dc 20 pulse 0 20 0 1u 1u 108u 2m
vd drain 0 dc 10 pulse 0 10 0 1u 1u 2m 4m
vcom com 0 dc 5

mntft drain gate ito ntft w=20u l=5u
cst ito com 1.06p
re ito co 1.28k
c0 co lc 317f
rlc lc com 10g
clc lc com 125f

cgs gate ito 20f
cgd gate drain 20f

.tran 0.1u 8m
.save v(drain) v(gate) v(ito)
.end

Figure 6. SmartSpice simulation of pixel.

 

 

Conclusion

The CLEVER’s accurate 3D field solver can be applied to TFT-LCD design to predict origin of various coupling capacitance and so crosstalk.

The process variation such as passivation layer and the configuration of electrodes is easily simulated by CLEVER. From the integrated prospect point of view, Silvaco’s CLEVER-SmartSpice supply good framework for future full-panel design.

 

Appendix

  1. J.S. Lin , Jpn J.App. Phys. Vol43, No.4A, 2004, p1476-1480
  2. Y. Z. Muju Li, IEEE Trans. ED vol.48, No.2, Feb. 2001,p218
  3. Webster E. Howard, IEEE Trans. ED, vol.36,No.9, Sept. 1989, p1938
  4. H.S. Chang, LCD R&D Center, LG-Philips LCD, Korea IDW’ 2005

 

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