STELLAR – Process Based Parasitics Capacitance Extraction on Large Custom Cells : Overview and Features

 

I Introduction

SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design. Indeed based on the success of CLEVER and EXACT, SILVACO wants to provide to customers tools with the same accuracy as the previous ones but dedicated to bigger layouts. It is becoming increasingly clear that with current designs around 0.1um parasitics are more and more important to take into account. Designers have to make an important decision whether to have verification either very precise using tools like CLEVER on relatively small layouts [1] or using classical LPE tool like HIPEX [2] which are known to be sometimes not accurate enough. Between them a wide gap lies and the aim of SILVACO new products is to fill it. These new tools keep the same famous in-house trends so-called TCAD driven CAD which means that as a fundamental core a 3D process simulator and a 3D field solver are the basis for an accurate parasitics extraction today.

This article will illustrate the architecture and the applications of STELLAR our new Fast Capacitance Parasitics Extractor Software and we will compare results to the field solver reference on the market CLEVER.

 

II STELLAR Architecture

Parasitic extraction accuracy is crucial for deep submicron designs. The targeted accuracy has been considered to be 3D Field Solver based. STELLAR reaches this goal by using a combination of 3D process and 3D field solver capabilities. The 3D process simulation allows the geometry of the final structure to be very accurately generated. Once the geometry is generated, a 3D topology of the layout is obtained. This is essential for accurate parasitic extraction for deep and ultra deep submicron technology.

This combination also allows STELLAR to be a powerful and flexible solution for extracting highly accurate parasitic capacitances in deep submicron designs summarized in the following chart. Note the architecture of STELLAR (Figure 1) is identical to that of CLEVER and QUEST. However the process simulator and the field solver are different.

Figure 1. The Parasitic Extraction Overview in CLEVER.

 

Capacitances are calculated from the distribution of charge density on the surfaces of conductors. Classically one can solve partial differential equations on the potential which can be done using finite difference or finite element methods. The normal derivative of the potential on the surfaces gives the charges acquired for capacitance calculation. The resultant matrix is sparse but large because the whole dielectrics volume is discretized. A very good 3D tetrahedral mesh is thus needed to solve this problem. Arbitrary conductor shapes and non-homogeneous structures can be handled. This is typically CLEVER.

A new method [3] is used in STELLAR. The meshing of a complex 3D domain is avoided by the use of two different meshes: a regular 3D grid on the whole domain and a surface mesh on the conductors. Due to this specific grid algorithm (volume + surface) the resultant matrix is sparse and a fast solver can be used to solve this system at low memory cost. The typical type of structure able to be simulated is planar and Manhattan. However, dummy metal simulations are also available [4].

 

III Product Overview

STELLAR exhibits the standard graphical user’s interface used in our DISCOVERY range of products (from QUEST, EXACT to QUEST3D), which eases its handling like all SILVACO software, which have been known to be intuitive and very easy to start with. The main steps to follow to define a complete parasitics capacitance extraction, from layout input, to final parasitics netlist extraction (note that all the pictures are from the GUI, but one can be done by more advanced users through batch mode) are now discussed.

When invoking STELLAR, the main STELLAR window shows up (Figure 2) and exhibits all the sequential steps that must be completed in order to extract the parasitic capacitances netlist.

Figure 2. Main STELLAR window.

The first step consists in describing the backend process flow, by indicating the material properties (conductivity for conductors and permittivity for insulators) and thicknesses. All of these parameters can be defined as variables allowing process variation experiments to be performed (Figure 3).

Figure 3. STELLAR process window.

The second step is the layout input to STELLAR, which can handle GDSII standard.

Eventually, the technological files required for netlist extraction need to be inputted. These may consist of derived layer generation, layer connectivity and device recognition. The actual device extraction performed on the layout is actually achieved using HIPEX-NET [2].

The next stage is the definition of the required accuracy for computation. After this has been completed STELLAR has all the relevant data to generate the 3D structure that will be meshed to extract parasitic capacitances.

Two types of data can be outputted according to the user’s wish: the 3D backend structure for topology checking purpose, and/or the parasitics netlist.

STELLAR also exhibits a very powerful feature, consisting of a built-in design of experiment (DOE) library. The available ones are: stepped, full or half factorial, box Behnken, circumscribed or faced central composite, linear and Gaussian random and Latin hypercube. This allows a large choice in the variation method, accordingly to the required range.

After having selected the type of DOE variation the simulation can be carried out automatically accordingly to the selected DOE, and the results (both 3D structure and parasitics netlist) stored in separated directories for subsequent use.

 

IV Simulation Results and Validation

STELLAR is targeted to simulate larger structures than the ones simulated by CLEVER [4]. An example of this is a multi stage inverter ring oscillator that has been simulated with STELLAR (Figure 4).

Figure 4. Multi inverters ring oscillator layout

Once the process and technological files are parsed, the 3D interconnect structure that is to be meshed is generated and then subsequently used by the solver (Figure 5).

 

Figure 5. Backend 3D structure used by STELLAR.

The parasitic capacitance netlist is then computed, and merged to the netlist extracted by HIPEX-NET thus having the devices extracted from the input layout. The final netlist is then ready to be used by SmartSpice or any compatible SPICE simulator, for signal integrity analysis or delay analysis, as shown in Figure 6.

Figure 6. SmartSpice transient analysis
of the 34 stages inverters ring oscillator.

In order to validate STELLAR, its output and simulation time are compared to a simulation using CLEVER. CLEVER is a widely well accepted tool for field solver applications and is considered to be our reference for parasitics extraction [5].

Since CLEVER cannot handle the full layout, the elementary inverter used in the full ring oscillator is extracted, and simulated. The issued netlists with both active and parasitics elements are then embedded into a SPICE subcircuit, duplicated 34 times and simulated with SmartSpice. This approach is sensible, since the complete layout is highly symmetrical, and CLEVER boundary condition set to ‘cyclic’ to be consistent with the layout topology.

A table summarizing the simulated results from STELLAR and CLEVER is shown below.

  STELLAR CLEVER
Delay (ps) 56.6 56.6
Simulation time (min) 52 47
Memory requirements (Mb) 245 425

 

Both STELLAR and CLEVER simulations were run on an Ultra 10 SPARC machine, with 1 Gb of RAM. One can see that the STELLAR simulated values are in very good agreement with thus obtained using CLEVER. One can also notice the STELLAR simulation time is similar for simulating the full layout composed of 34 inverters than the CLEVER simulation time for simulating only one inverter. This exhibits the very efficient algorithm implementation and robustness. One can also see the memory requirements are 40% less compared to CLEVER for simulating a structure 34 times wider!

The second stage of STELLAR’s validation used two other layout simulations.

These layouts were also ring oscillators made of chained inverters, but with different layout configurations. The 3D backend structure for each basic inverter is given in Figures 7.a and 7.b. The first structure, (Figure 7.a), layout 1 was designed in the same way as the previous one, with the idea of maximizing parasitic capacitances between the input and the output of the inverter stage (which is obviously the worst case for transit delay time).

Figure 7a. Basic stage inverter (plate coupling)

Figure 7b. Basic stage inverter (reference inverter)

The second layout, Figure 7.b, layout 2 was used as the reference for transit time (i.e. not increasing capacitive coupling in the layout).

The following table sums up the mean time delay per inverter.

  STELLAR CLEVER
Layout 1 59.2 ps 58.1 ps
Layout 2 45.9 ps 43.4 ps

One can observe that again, STELLAR is able to handle such layouts associated to complex back end processes. Simulation results from the two solvers are in good agreement.

 

V Comparison with the Other DISCOVERY Framework Tools

The DISCOVERY framework provides various tools in order to fulfill user needs. This range is composed of the following:

  • CLEVER is an accurate process based parasitics solver, which allows the extracting of parasitic netlist (both resistors and capacitors) over custom library cells.
  • EXACT is used to provide capacitor models for Layout Parasitic Extractor (LPE) tools. It is based on the CLEVER simulation tool and is therefore process based and field solver based [6].
  • QUEST is designed to extract frequency dependent transmission-line SPICE models [7] [8].

In order to validate the STELLAR results with the remaining tools in the DISCOVERY suite, a common structure has been designed for these three parasitics extraction tools, and the simulated results compared.

Figure 8 gives the structure cross section that has been used. This is a typical interconnect pattern, with three parallel lines over silicon wafer. Spacing ’S’ between the three lines is defined as a parameter and ranges between 0.25 um and 3um. Three capacitances are plotted (Figure 9), these are described as:

  • Css is the capacitance between the middle line and the substrate
  • Csa and Csb are the coupling capacitances between the respective outer line and the middle conductor

Figure 8. Three lines structure cross section.

 


Figure 9. Comparison between STELLAR, CLEVER and QUEST

One can see that despite the fact that these three tools use three different numerical methods and meshing strategies, the computed values are very close to each other.

In Figure 9 the three capacitances between the lines and the substrate as described previously are plotted. As expected, since the structure is symmetric, both external lines exhibit the same capacitance value whatever the distance between 2 lines is (only one capacitance variation is plotted for clearity). The shape of these curves are as expected, the inverse ratio of the distance between the conductors facing each other. On the other hand, the middle line capacitance with the substrate varies less than the coupling capacitances, since distance to the substrate is kept constant. Its variation is due to the outer lines, channeling more or less electric field lines according to the distance to the middle line.

This comparison of the three tools gives an insight to the accuracy of the TCADbased approach followed by SILVACO.

 

VI Targeted Structures for STELLAR

As demonstrated in the previous case study, STELLAR is targeted to handle much larger circuits than CLEVER. Thanks to its new meshing and numerical schemes, accuracy is not given up to computation speed, and simulation results are in very good agreement with electrical measurements as demonstrated previously.

 

1) STELLAR New Features

STELLAR exhibits some new interesting features, which allow larger layout to be simulated. Here is a quick overview of these new functions.

The main issue with simulating large structures is obviously memory requirements. Two different techniques have been used to optimize this aspect of the simulation.

Keeping in mind that the final goal is to extract a capacitance between two conductors, a new parameter called ‘effect length’ has been set, which sets the distance above which the possible couplings will be considered to be insignificant. Let’s call this variable ‘D’. The solver will define iteratively a halo all along each conductor with the distance ‘D’ wrapping the considered conductor, which will determine which other conductors to take into account for capacitance calculation (all other ones will be considered being too small). This will strongly reduce domain calculation size for each conductor.

This methodology is illustrated on Figure 10, where the distance effectiveness is drawn on conductor (1). One can see that only part of conductor (2) lies within the halo, and thus only the capacitance between conductors (1) and (2) will be calculated, capacitance between (1) and (3) being considered negligible and eventually not included in the netlist.

Figure 10. Halo filtering illustration

The other technique consists in cutting the full layout into smaller parts, computing the capacitances into each domain, as well as domain boundary conditions to use for the adjacent parts (Figure 11). This technique is called domain decomposition. Its main advantage, used in conjunction with the ‘halo’ calculation, is to reduce the mesh to input to the solver, and then allow using very large layouts.

 

Figure 11. Domain decomposition methodology.

 

The other main advantage, thanks to ‘halo’ calculation, lies upon the fact that on certain domains, no capacitance calculation will occur, since no conductor will lie within the halo.

 

2) STELLAR New Features Validation

In order to validate the concepts used in STELLAR, some simulations have been carried out using or not domain decomposition and/or using or not the ‘halo filtering’ method. This has been applied to the ring oscillator presented previously.

The first simulation consisted in inputting the entire layout at once. Both domain decomposition (DD) and halo methodology unset. The next simulation has been done with the STELLAR default parameters, i.e. automatic selection of DD, halo methodology set.

All the extracted netlists have been inputted to SmartSpice. The following table sums up the simulation results obtained.

 
Maximum memory used (Mb)
Simulation time (min)
Delay (ps)
No DD, no halo
154
120
57.3
DD+halo
245
52
56.6

One can observe from this table that both methods give the same delay per inverter. Thanks to domain decomposition method, used in conjunction with the halo filtering, one can observe that the simulation time is decreased by almost 5 times, the maximum memory size being constant (boundary conditioning management).

The other interesting feature is that thanks to halo filtering, the computed parasitic capacitance netlist is much smaller than computing the full structure at the same time. To give an idea on the SPICE netlist reduction, with DD and halo filtering, there are 172 computed capacitances, whereas there are 634 with the classical methodology (no DD, no halo filtering). One can immediately see the advantage of the filtering, not only considering the netlist reduction, which can be achieved by other external tool like netlists reductors, but the RELEVANT netlist calculation at the solver level, which ONLY computes capacitances being influent for the SPICE simulation.

Setting these options gives the users the insurance of having the most optimized parasitics capacitance netlist (on the part number level), allowing thus fast SPICE computations not giving up accuracy to computation speed.

 

3) STELLAR New Features

In order to give an idea of STELLAR’s potential and efficiency, a large layout has been inputted to STELLAR (50*40 um2). Interconnect density is very high (Figure 12), and this technology features four interconnection layers.

Figure 12. STELLAR generated 3D backend structure.

This layout has been used with its technology file as input to STELLAR, and the cell’s backend topology simulated. This structure exhibits state of the art technology, since in this example case, one can see that several conducting materials can be used (polysilicon, aluminum, copper…), as well as any intermetallic dielectric material (not shown in the 3D picture), and 45 degrees angled routing metallization (Figure 13).

The next picture shows a zoom over the backend structure side. Meshing has been overlaid to the interconnect structure (Figure 13).

 

Figure 13. STELLAR meshing.

 

The parasitics netlist has been computed in less than 55 minutes for this structure with a maximum memory use of 121Mb.

Another large layout has been inputted to STELLAR, with an even larger size (153x113 um2).

Due to the large size of the layout, and the complex process used for generating the 3D backend process (4 metallization layers in this case plus multi dielectric materials), this structure will take advantage of the halo filtering technique and domain decomposition methodology. Such a large structure, with more than 5000 transistors has been successfully simulated with STELLAR, giving the parasitics netlist (more than 40000 capacitances) in 36 hours, with a maximum memory use of less than 1Gb.

 

Conclusion and Perspectives

This paper has demonstrated STELLAR’s ability to extract parasitic capacitances from large layouts. The numerical scheme and new meshing algorithm efficiency has been emphasized through comparisons with already existing SILVACO tools (QUEST, CLEVER) and with measurements over manufactured devices.

This validates STELLAR initial targets, i.e. handling structures bigger than the ones input to CLEVER, and smaller than the ones the full chip extractor HIPEX uses.

This does not mean that this TCAD based approach has to be limited to middle range layouts, and that’s why the input range is being extended, since the next target is to develop a parallel scheme that will allow STELLAR to input even larger layouts.

 

Acknowledgements:

SILVACO wishes to thank LETI for its collaboration to this work.

 

References:

  1. Validation of CLEVER Interconnect Parasitics with 0.18um Process Measurements, Simulation Standard Volume 9, Number 11, November 1998.
  2. HIPEX–Hierarchical Layout Parameter and Parasitic Extractor, Simulation Standard Volume 13, Number 3, March 2003.
  3. Calcul des Capacites Parasites dans les Interconnexions des Circuits Integres par une Methode des Domaines Fictifs, Ph.D. Thesis, Sylvie Puteaux, 2001.
  4. An Efficient Algorithm for 3D Interconnect Capacitance Extraction Considering Floating Conductors, O. Cueto, F. Charlet, A. Farcy, pp.107-110, Proceedings SISPAD 2002.
  5. B. FROMENT, et al., “New Interconnect Characterization Method for Multilevel Metal CMOS Processes”, ITTC may 1999.
  6. EXACT2: Interconnect Parasitic Capacitance Simulator from Silvaco, Simulation Standard Volume 13, Number 2, February 2003.
  7. QUEST Extraction of Frequency Dependent R, L, C, and G Transmission Line Models, Simulation Standard Volume 11, Number 5, May 2000.
  8. QUEST: Frequency-Dependent RLCG Extractor Part 2 - Comparison with Experiments, Simulation Standard Volume 12, Number 5, May 2002.

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