Electrostatic Effect of Localized Charge in Dual Bit Memory Cells with DiscreteTraps


L. Perniola(1, 2,*), S. Bernardini(3), G. Iannaccone(1,6), B. De Salvo (4), G. Ghibaudo (2), P. Masson(3), C. Gerardi(5)

(1)Dipartimento di Ingegneria dell’Informazione, Università degli Studi di Pisa, Via Caruso, 56122 Pisa, Italy, *perniola@enserg.fr
(2)IMEP-CNRS/INPG, Avenue de Martyrs 32, 38016 Grenoble, France
(3) L2MP-Polytech – IMT Technopôle de Château Gombert, 13451 Marseille Cedex 20 France
(4)CEA-LETI, Avenue de Martyrs 16, 38054 Grenoble, France
(5)STMicroelectronics, Catania, Italy
(6)IEIIT-CNR, Via Caruso, 56122 Pisa, Italy.

The following article, presented at ESSDERC 2004 conference, illustrates the capability of ATLAS in the validation and the comprehension of complex effects of new and promising devices like non-volatile discrete trap memory devices.

Abstract

In this paper the electrostatic impact of Channel Hot Electron (CHE) injection in discrete-trap memories is quantitatively addressed. The dual bit behavior of the transfer characteristic during forward and reverse read of a written cell is thoroughly analysed with the help of an analytical model. Such model allows, for the first time, to estimate the effective charged portion of the discrete storage layer, L2, and the quantity of electrons, Q, injected in the trapping sites from the experimental parameters of the Id-Vg characteristics, the reverse-forward threshold voltage shift VRF, and the total threshold voltage shift Vtot. The viability of this model is confirmed with tests performed on nanocrystal memories, under different bias conditions. These results are confirmed with the help of a 2D drift-diffusion commercial code (ATLAS-SILVACO).

 

1. Introduction

Channel Hot Electron injection is widely used as a standard writing method for non-volatile discrete-trap memory products [1]-[2]. It provides the opportunity to localise the charges injected in a small region of the trapping medium, and two-bit operation is achieved through multilevel storage [3]. The basic principle on which two-bit operation resides, is common to NROM memories and nanocrystal memories [4]-[5]. It is possible to trap charges near one junction (drain or source) with a programming stress, and read them in the reverse mode, compared to the programming, enhancing the electrostatic effect of these charges on the conductivity of the active channel (see Figure 1).

It has been shown in the literature [1]-[3]-[6] that the threshold voltage during the forward read, Vth-F, is lower than the threshold voltage during the reverse read, Vth-R, when the cell is polarised in the saturation regime.

This is due to the strong two dimensional effects near the charged junction. If the injected charge, near the drain, is completely screened by the high Vds applied in forward read (which induces a long pinchoff region), the Id-Vg characteristic results very close to the characteristic of the fresh cell. In this case we have a low Vth-F. On the other hand, during the reverse read the high Vds applied is not able to screen the effect of electrons and the conductivity of the active channel is lowered by the “bottleneck” near the low-voltage contact. In such a case we have a high Vth-R [2]-[6].

Figure 1. The concept of forward and reverse read after Channel Hot Electron programming, considering a non zero bulk potential. In the figure the depletion width under the charged and uncharged regions is highlighted.

 

With a simple 1D approach (Gradual Channel Approximation) [6] it is not possible to simulate such an asymmetric behavior. In this paper, with the help of a simple quasi 2D analytical approach, we are able to quantify for the first time, both the length of the charged region, L2, and the number of injected electrons per unit area in the trapping sites, Q, from the two quantities available from experiments, the total threshold voltage shift, Vth-tot, (i.e., the difference between the threshold voltage in the reverse read, Vth-R, and the threshold voltage of the fresh cell, Vth-fresh) and the reverse-forward threshold voltage shift, VRF (i.e. the difference between Vth-R and Vt-F).

The viability of the model is tested with 2D numerical simulations of a commercial TCAD code (ATLAS-SILVACO).

Main results from the theory are widely tested, under different bias conditions, on nanocrystal memories fabricated by ST-Microelectronics [4]. The influence of the bulk potential, as well as that of the drain-to-source potential, are carefully assessed in this work.

 

2. Quasi-2D Analytical Model

With a simple 1D approach it is not possible to describe properly the 2D effects near the charged region, which are the first cause of the dual bit behavior. For the first time, to our knowledge, we present an analytical approach, which starts from quasi 2D considerations [7].

The analytical approach describes the behavior of the surface potential S along the channel of a MOSFET with non-uniform threshold voltage. The distribution of trapped charge may be in general a complicate function of the spatial coordinates. We assume that the charge distribution along the channel can be described by a step function which represents an “effective” distribution. As a result, we can distinguish two regions: one close to the source with a length L1, where storage nodes are not charged (uncharged region); and the second one close to the drain with a length L2 which is uniformly charged by Q electrons per unit area. In Figure 2 it can be seen how the written memory is divided in the two regions. The trapped charge raises the flat band voltage, Vfb-2, of the charged region L2. In particular the flat band voltage difference between the charged and the uncharged region is:

Where q is the electron charge, C2 is the top oxide capacitance per unit area.

Figure 2. Sketch of the charged and uncharged regions. Equation (2) and (3) come from the Gauss’ law applied to the two slices of thickness dy. Boundary conditions are shown (Vbi is the built-in potential), considering the presence of a bulk voltage Vb. The potential reference value is the Fermi level of the bulk.

 

In the following model, we do not consider charges over the drain junction, but, as already noted by [6], from Figure 3 it appears that they do not influence Id-Vg characteristics.

Figure 3. ATLAS simulations to assess the influence of charge over drain junction. It is clear that a charged region over the junction of length comparable to L2, has negligible effects on channel conductivity.


The model solves separately, in the two regions, the differential equations (2) and (3). Gauss’ law is applied to a transversal slice of thickness dy along y and cross section equal to the average depletion width Xdep1(i=1,2) (see Figure 2), and allows us to write the flux of the electric field through the faces perpendicular to y in terms of the surface potential as (Xdep1/h)ds/dy, where is a fitting parameter. During the gate voltage sweep, frequently the uncharged region goes in strong inversion, while the charged region is still pinched-off. The presence of both inversion charge Qinv and depletion charge at inversion Qdep1, are carefully considered in Equation (3):


where si (ox) is the silicon (oxide) electric permittivity, Vg the gate voltage, tox is the equivalent oxide thickness, Nsub is the doping level of the bulk. If a bulk voltage, Vb, is applied, as sketched in Figure 2, the drain, source and gate potentials must be raised of Vb, setting at zero the potential of the bulk. The space charge and the inversion charge have the following expression:

Where i=1,2, L-i is the surface potential in the case the influence of drain and source junctions is completely neglected, Ucs is the quasi-Fermi potential referred to the source of the uncharged equivalent transistor.

The solution to Equation (2) is a linear combination of hyperbolic sins:

where r-1 (l-1 ) is the right-hand (left-hand) boundary condition shown in Figure 2. s-1 is referred to the value of the potential in the bulk. The solution to Equation (3) is of similar form of Equation (6).

The parameter describes the short channel effects, as it provides a clue on how strong is the influence of the junction potential on s under the gate. The higher the value of l, the smoother appears the s curve along the channel, the weaker is the control effect of the gate on the channel.

From the description of the surface potential, the drain current can be calculated. As in the subthreshold region the current is a diffusion dominated process, the following expression can be derived [8]:

where µeff is the effective mobility of electrons in the channel, KT is the thermal energy, ni is the intrinsic electron concentration in silicon and Smin is the minimum of the surface potential in the channel.

 

3. Comparison Between the Analytical Model and ATLAS Results

From Equation (2), the importance of h is apparent.

To determine the proper value of this parameter, we have used the commercial TCAD tool ATLAS from SILVACO. We have simulated a class of nanocrystal memories, fabricated from STMicroelectronics. Parameters of the memory cell are L=0.28 µm, W=0.16 µm, tunnelling oxide thickness ttun-ox=5.5 nm, control oxide thickness t2=8 nm. The charged nanocrystals have been considered as a uniform charged oxide region, of thickness tch=2 nm, sandwiched between the tunnelling oxide and the control gate oxide.

Figure 4 (a) Comparison of the transfer characteristics from ATLAS (solid lines) and analytical model (circles) to extract the value of the fitting parameter . In the case of L2=L/4, the best value is =4. (b) Comparison of Vth versus Q obtained with ATLAS (solid lines) and the analytical model (circles) shows that is weakly dependent on the density of electrons injected in dots. In the inset of Figure 4(b) the dependence of on L2 is provided.

 

Figure 5. Reverse-forward threshold voltage shift VRF as a function of the charged length L2 obtained from ATLAS (circles) and the analytical model (solid line). Parameters are dot density 1012 cm-2, 6 el./dot and according to the inset of Figure 4(b).

 

As specified before, we simply assumed that the charge distribution in the oxide is a step function where the charged length can be varied and the density of charge has been chosen to fit different flat band voltages Vfbs.

In Figure 4(a) a sample comparison between ATLAS results and the analytical model for L2=L/4 is shown. The parameter h to fit Id-Vg numerical characteristics has shown a weaker dependence on the density of electrons trapped in dots, Q, than on the charged length L2. This property is shown in Figure 4(b), where, provided one value of L2, it is possible to fairly fit different values of Q, with one value of . In the inset, on the other hand, the dependence of on L2 is provided (strong dependence of on L2).

Figure 6 . Reverse-forward threshold voltage shift VRF as a function of the density of electrons Q obtained from ATLAS results (circles) and the analytical model (solid line). Parameters are L2=L/8 (35 nm) =3 and L2=L/4 (70 nm) =4 (according to the inset of Figure 4(b)).

 

Already the plot of Figure 4(a) shows that the forward and reverse bits are not clearly detached for L2=L/4 (L2=70 nm), and cannot be easily sensed as Vth-F and Vth-R are similar. From Figure 5, it is clear that one-bit operation appears for L2>70 nm (VRF0V). It is not required that the whole region of the channel is uniformly charged to have Vth-FVth-R.

Another interesting property is the charge density insensitivity of VRF, once a saturation limit is achieved.

In Figure 6 such a behavior is shown for L2=L/8 (L2=35 nm) and for L2=L/4 (L2=70 nm). In the case of L2=L/4, for Q>2x1012 el./cm2 the window between the forward and reverse threshold voltage is almost constant; while in the case of L2=L/8, this property appears for Q>5x1012 el./cm2. Therefore VRF can be used as an absolute indicator of the charged region dimension.

 

4. Comparison Between the Analytical Model and Experiments

Figure 7. Analytical model vs data obtained from nanocrystal memories as a function of drain-to-source Vds reading voltage.

 

Experiments performed on STMicroelectronics nanocrystal memory cells [4] confirm both the validity of the analytical model and suggest how to perform a reading procedure which allows to enhance the asymmetry between forward and reverse read.

Figure 8. Analytical model versus experiments obtained from nanocrystal memories with Vds=1.5V and different bias condition for Vd.

 

From Figure 7, it is clear that raising Vds enhances the electrostatic effect of trapped electrons, and decreases Vth-F to the value of the fresh cell threshold voltage, Vth-fresh. In experiments the maximum reading Vds has been put at 1.5V. In Figure 8, the viability of this analytical model with different bulk voltages, Vb has been tested. The most relevant conclusion of this work is presented in Figure 9. As an example it is shown a contour plot of Vtot(L2,Q) and VRF(L2,Q) that can be calculated from this model. From the two experimental parameters Vtot (blu line) and VRF (red line) is possible to find in the contour plot the crossing point and then deduce the values of V2 and the density of electrons Q injected in the trapping medium.

 

5. Conclusions

A detailed model concerning Channel Hot Electron (CHE) electrostatic impact on forward/reverse reading has been provided. Both numerical simulations and experiments on nanocrystal memories, performed under different bias conditions confirm the viability of the model. At our knowledge, for the first time in literature, a contour plot is provided (Figure 9) where, from the experimental results at hand (Vtot and VRF), it is possible to assess the effective charged length, L2 and the density of injected electrons, Q. Support from EU projects ADAMANT (IST-2001-34234), SINANO (IST-506844) and from the CNR through the FIRB project is gratefully acknowledged.

 

References

  1. B. Eitan, IEEE El. Dev. Lett., 21, 11, Nov. 2000.
  2. E. Lusky, IEEE El. Dev. Lett., 22, 11, Nov. 2001.
  3. I. Bloom, Microel. Eng., 59, 2001, 213-223.
  4. B. DeSalvo, Proc. of IEDM 2003.
  5. B. Muralidhar, Proc. of IEDM 2003.
  6. L. Larcher, IEEE Trans. El. Dev., 49, 11, Nov. 2002.
  7. Z. H. Liu, IEEE Trans. El. Dev., 40, 1, Jan. 1993.
  8. Y. Taur, “Fundamentals of Modern VLSI Devices”, CUP, 1998.

 

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