IBIS Models in SmartSpice

1. Introduction

The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines...) on printed circuit boards (PCBs).

The IBIS standard offers a way to provide fast and accurate models of I/O buffers without divulgating any proprietary technology process. As it protects IP, it is now widely used by semiconductor vendors as a replacement for SPICE netlists. The IBIS standard specifies only what kind of information is provided, how this information is presented in ASCII files and how some data are derived from measurements or simulations. How these data are used and processed by a simulator is not part of the standard. The purpose of this documentation is to present the IBIS model support in SmartSpice.

The reader who is not familiar with the IBIS standard or would like to learn more about IBIS may refer to the Web site of the IBIS Open Forum at http://www.eigroup.org/ibiswhere numerous documents are available for download, including introductions, slide shows, articles and complete specifications (from the initial v1.0 to the latest v4.1 of January 2004).

 

2. IBIS Buffer Equivalent Circuit

A buffer is implemented as a new element in SmartSpice. Even though different types of buffers are available to cover a wide range of functions and technologies, they are all base on the same equivalent circuit, which is shown on Figure 1.

Figure 1. IBIS Buffer General Circuit Diagram.

 

Several elements and terminals are optional depending on the buffer type: Input (node IN) and Enable (node EN) high-impedance inputs, Output (node OUT) voltage source and conductance, Pullup/Pulldown (nodes PU/PD) Voltage-Controlled Voltage Sources (VCVS). Only Input/Output buffers have all elements and all terminals available. The number of terminals and the description of the equivalent circuit are given in Table 1 for all buffers currently supported in SmartSpice.

Type/Number
Terminals (min/max)
Input
Enable
Output
Pullup
Pulldown
input/1
4
no
no
yes
no
no
output/2
4/6
yes
no
no
yes
yes
input_output/3
6/8
yes
yes
yes
yes
yes
three_state/4
5/7
yes
yes
no
yes
yes
open_drain/5
4/6
yes
no
no
no
yes
io_open_drain/6
6/8
yes
yes
yes
no
yes
open_sink/7
4/6
yes
no
no
no
yes
io_open_sink/8
6/8
yes
yes
yes
no
yes
open_source/9
4/6
yes
no
no
yes
no
io_open_source/10
6/8
yes
yes
yes
yes
no
input_ecl/11
4
no
no
yes
no
no
output_ecl/12
3/5
yes
no
no
yes
yes
io_ecl/13
5/7
yes
yes
yes
yes
yes
three_state_ecl/14
4/6
yes
yes
no
yes
yes

Table 1. Description of the equivalent circuit for all buffer types.

The Gnd node corresponds to the SPICE ground node, also called node 0. All connections to Gnd are internal (C_comp, Vout...) and so this node is not available as a terminal. The die capacitance C_comp specified in IBIS models is usually connected between IO node and ground. However, if die capacitances C_comp_pc, C_comp_gc, C_comp_pu and C_comp_pd are specified in the IBIS model instead of C_comp, these four capacitances are connected between IO and PC, GC, PU and PD nodes, respectively.

PC/PU and GC/PD terminals are usually supposed to connect to power and ground rails, respectively. By default they are connected to internal voltage sources (not shown on the circuit diagram) and should not be connected to any other elements in the netlist (especially voltage sources). However the instance parameter power may be used to allow connections to external elements or power supplies.

 

3. IBIS Buffer Device Line

Using buffers in SmartSpice is identical to using other elements like passive or semiconductor devices. The general syntax of a buffer statement is given by:

Bname term1 term2 term3 [term4 [term5 [term6 [term7 [term8]]]]]
+ file = ‘filename’ model = ‘modelname’
+ [typ = {typ|min|max|fast|slow}]
+ [power = {on|off}]
+ [interpol = {1|2}]
+ [buffer = {number|type}]
+ [ramp_rwf] = {0|1|2}
+ [ramp_fwf] = {0|1|2}
+ [fwf_tune = value] [rwf_tune = value]
+ [c_comp_pc = value]
+ [c_comp_gc = value]
+ [c_comp_pu = value]
+ [c_comp_pd = value]

 

Device naming convention

The buffer element name must begin with B followed by optional alphanumeric characters.

 

Terminals

The number and the order of terminals specified on the device line are type-dependent:

B_input PC GC IO OUT (Input and Input_ECL)

B_output PU PD IO IN [PC [GC]] (Ouput, Open_drain, Open_sink, Open_source)

B_three_state PU PD IO IN EN [PC [GC]] (Three_state)

B_input_output PU PD IO IN EN OUT [PC [GC]] (Input_output, IO_open_drain, IO_open_sink and IO_open_source)

B_output_ecl PU IO IN [PC [GC]] (Output_ecl)

B_io_ecl PU IO IN EN OUT [PC [GC]] (IO_ecl)

B_three_state PU IO IN EN [PC [GC]] (Three_state_ecl)

Open_drain, IO_open_drain, Open_sink and IO_open_sink buffers have no pullup circuitry but PU terminal must be specified even though not connected to internal elements. Open_source and IO_open_source buffers have no pulldown circuitry but PD terminal must be specified even though not connected to internal elements.Ouput_ecl, Three_state_ecl and IO_ecl buffers have pullup and pulldown circuitry but no PD terminal because this latter node is internally connected to PU node.

 

Required Parameters

file and model are required parameters to define the location of the .ibs file containing the IBIS model for this buffer. In SmartSpice these parameters are also used to decide if a B statement corresponds to a MESFET device or to an IBIS buffer. See Backward Compatibility paragraph below for further details.

  • ‘filename’ is case-sensitive and must correspond either to the absolute path to the .ibs file or the relative path in respect to the directory where SmartSpice is run or to the directories specified by the option ‘d_ibis’. See Options paragraph below for a description of this new option
     
  • ‘modelname’ is case-sensitive and must match one of the models in the .ibs file

 

Optional Parameters

typ must be set to select what column of all IBIS data will be used during the simulation: TYP (default), MIN, MAX, SLOW or FAST. If FAST or SLOW are specified, the column MIN or MAX is selected depending on the IBIS parameter as defined in table 2. This is especially useful for best case / worst case analysis. If min or max values are not available in the IBIS model for a given parameter, typ values are used.

IBIS Parameter/Data
Fast
Slow
C_comp
min
max
C_comp_pc
min
max
C_comp_gc
min
max
C_comp_pu
min
max
C_comp_pd
min
max
Voltage_range
max
min
Pullup_reference
max
min
Pulldown_reference
min
max
Power_clamp_reference
max
min
Gnd_clamp_reference
min
max
Pulldown
max
min
Pullup
max
min
Gnd_clamp
max
min
Power_clamp
max
min
Ramp
max
min
Rising_waveform
max
min
Falling_waveform
max
min
V_fixture
max
min

Table 2. Min/Max combinations for Slow/Fast conditions.

power is used to select how the buffer is powered via PC, GC, PU and PD nodes (if these latter nodes exist for the given buffer type).

  • If power is set to ‘on’ (default), these nodes are internally connected to voltage sources whose values are taken from the IBIS parameters: [POWER Clamp Reference], [GND Clamp Reference], [Pullup Reference], [Pulldown Reference] (or [Voltage Range] if preceding parameters are missing). For this case, terminal names specified on the element card may be usefull to print out the voltage values if needed
     
  • If power is set to ‘off’, internal voltage sources are not created and PC, GC, PU and PD nodes must connect to external voltage sources either directly or through passive devices like RLC networks or transmission lines.

interpol is the interpolation method selector.

  • If interpol is set to 1 (default), I/V curves are interpolated using linear interpolation
     
  • If interpol is set to 2, quadratic bi-spline interpolation is used. This latter method is usually not recommended and useless anyway if IBIS data are accurate

buffer is used to specify the type of the buffer. This value overrides the corresponding IBIS parameter Model_type. It is usually not recommended to specify a different value. Integer values are allowed to select a buffer. The correspondence with literal names is given in table 1.

ramp_fwf and ramp_rwf selectors allow the user to choose the calculation method of multipliers Ku(t) and Kd(t). These parameters are totally independent and may have different values.

  • If ramp_fwf (or ramp_rwf) is set to 0 (default), only the ramp data is used to derive multipliers for the falling (or rising) transition
     
  • If ramp_fwf (or ramp_rwf) is set to 1, the first falling (or rising) waveform table available in IBIS model is used to derive corresponding multipliers
     
  • If ramp_fwf (or ramp_rwf) is set to 2, the first two falling (or rising) waveform tables available in IBIS model are used to derive corresponding multipliers

These latter option is highly recommended to get accurate results in transient analysis. However, if the required data are not available in IBIS model, the value of ramp_fwf (or ramp_rwf) is decremented and a warning message is issued. For example, if ramp_fwf = 2 and only one waveform table is given, then ramp_fwf is set to 1, if ramp_fwf =1 and only ramp data are given, then ramp_fwf is set to 0.

fwf_tune and rwf_tune factors are control parameters for ramp_fwf =0, 1 and ramp_rwf = 0, 1 algorithms, respectively. When only ramp data or one waveform is available, it is necessary to impose an additional condition to compute multipliers. Usually it is assumed that Ku(t)+K(t)=1, which was demonstrated to be not realistic because the circuitry that goes from ON to OFF undergoes this transition faster than the circuitry that goes from OFF to ON.

By setting fwf_tune or rwf_tune to a value between 0 and 1 (default 0.1), it is possible to get more accurate transitions by using the following assumption: if deltaT is the duration of a complete transition, the multiplier K(t) corresponding to the circuitry that goes from ON to OFF decreases linearly from 1 to 0 between t=0 and t=fwf_tune * deltaT (or t=rwf_tune * deltaT depending on the transition). Thus, the other multiplier is uniquely determined from an IBIS ramp or one IBIS waveform. The multiplier computation methods are described in articles (1, 2).

C_comp_pc, C_comp_gc, C_comp_pu and C_comp_pd are dimensionless die capacitance partionioning factors. They do not override the IBIS parameters with the same names, which correspond to actual die capacitances. If these latter capacitances are specified in the IBIS model, the dimensionless factors are useless and ignored if given on the element card. If only C_comp is available in the IBIS model, it may be desirable to split it into several parts for simulating power/ground bounce. This is achieved by specifying the fractions of C_comp connected between IO node and PC, GC, PU, PD nodes. If given, the values of instance parameters C_comp_pc, C_comp_gc, C_comp_pu and C_comp_pd should be between 0 (default) and 1. It is also expected that their sum equals 1.

 

4. Buffer Logical State

The logical state of a buffer is controlled by the voltage of IO, IN and/or EN nodes relative to ground and noted Vio, Vin and Ven, respectively.

For buffers with no controlling signals (no IN or EN nodes), the state is a function of Vio, the IBIS parameters Vin_l, Vin_h (thresholds), Polarity and the previous state if any.

If Polarity=Non-Inverting

  • Initially (t=0 in transient analysis or first computed point of a DC sweep), state is set to LOW if Vio<(Vin_h+Vin_l)/2 or to HIGH in the opposite case
     
  • If state=HIGH then it goes to LOW only if Vio<Vin_l
     
  • If state=LOW then it goes to HIGH only if Vio>Vin_h

else Polarity=Inverting

  • Initially (t=0 in transient analysis or first computed point of a DC sweep), state is set to LOW if Vio>(Vin_h+Vin_l)/2 or to HIGH in the opposite case
     
  • If state=HIGH then it goes to LOW only if Vio>Vin_h
     
  • If state=LOW then it goes to HIGH only if Vio<Vin_l

For buffers with only one controlling signal (IN node), the state is a function of Vin, the IBIS parameter: Polarity and the previous state if any. Here thresholds are constant built-in parameters

If Polarity=Non-Inverting

  • Initially (t=0 in transient analysis or first computed point of a DC sweep), state is set to HIGH if Vin>0.5 or to LOW in the opposite case
     
  • If state=HIGH then it goes to LOW only if Vin<0.2
     
  • If state=LOW then it goes to HIGH only if Vin>0.8

else Polarity=Inverting

  • Initially (t=0 in transient analysis or first computed point of a DC sweep), state is set to HIGH if Vin<0.5 or to LOW in the opposite case
     
  • If state=HIGH then it goes to LOW only if Vin>0.8
     
  • If state=LOW then it goes to HIGH only if Vin<0.2

For buffers with two controlling signals (IN and EN nodes), the state is a function of Ven, Vin, Vio, the IBIS parameters: Vin_l, Vin_h (thresholds), Polarity, Enable and the previous state if any. The enable signal Ven supersedes the input signal Vin and is used to determine whether the buffer is in ENABLE or DISABLE state:

If Enable=Active-High

  • Initially (t=0 in transient analysis or first computed point of a DC sweep), buffer is ENABLE if Ven>0.5 or DISABLE in the opposite case
     
  • If buffer=ENABLE then it goes to DISABLE only if Ven<0.2
     
  • If buffer=DISABLE then it goes to ENABLE only if Ven>0.8

else Enable=Active-Low

  • Initially (t=0 in transient analysis or first computed point of a DC sweep), buffer is ENABLE if Ven<0.5 or DISABLE in the opposite case
     
  • If buffer=ENABLE then it goes to DISABLE only if Ven>0.8
     
  • If buffer=DISABLE then it goes to ENABLE only if Ven<0.2

If a buffer is ENABLE, the state is controlled by Vin according to the rules defined above for buffers with only one controlling signal (IN node).

If a buffer is DISABLE, there are two possible behaviors depending on the type:

  • For buffers without output circuitry (no OUT node), the state is just locked till the buffer returns to ENABLE. Three-state buffers belong to this family
     
  • For buffers with output circuitry (OUT node), the state is controlled by Vio according to the rules defined above for the buffers with no controlling signals. Input-output buffers belong to this family

The logical state can be printed out if the output circuitry (OUT node) is available:
If state=HIGH then Vout=1.0V. If state=LOW then Vout=0.0V.

OUT node can also connect to external elements, especially IN or EN nodes of other buffers. This nodes offer a simple way to create complex digital blocks in SPICE netlists.

 

5. Output Variables

The variables listed in table 3 can be printed out using the SmartSpice syntax @B_name[variable_name].

Variable name Definition
ku Pullup transient current multiplier
kd Pulldown transient current multiplier
cio Input/Output terminal current
cpc Power Clamp terminal current
cgc Ground Clamp terminal current
cpu PullUp terminal current
cpd PullDown terminal current
cin Input terminal current
cen Enable terminal current
cout Output terminal current

Table 3. Buffer internal variables.

 

6. IBIS-related Options

GMIN/DCGMIN conductances are connected in parallel with PC and GC diodes and with PU and PD Voltage-Controlled Voltage Sources (if they exist for the buffer type) to ensure better convergence of buffer devices in particular situations.

A new option d_ibis has been added to specify the location of .ibs files. Several paths can be specified. A .ibs file will be searched in all specified paths if the filename given on B statements is not an absolute path and is not found in the directory from which SmartSpice runs. This option is case-sensitive. For example:

.option d_ibis=’/home/mylogin/myIbisModels’

d_ib is also available as a variable and can be set in SmartSpice .ini files. For example:

set d_ibis = ( . /home/mylogin/myibismodels )

 

7. Backward Compatibility

In previous releases of SmartSpice, B statements were only used to define instances of MESFET models (as an alias of Z). From now on, they may also be used to define IBIS buffers. When a B statement is encountered in a netlist, SmartSpice first checks whether the IBIS-specific parameters file and model are specified in the element card. As these parameters are required to create an IBIS buffer, SmartSpice creates a MESFET device if they are missing, so that backward compatibility is maintained.

 

8. Limitations

  • Only DC, Transient and AC analysis are supported for IBIS buffers
     
  • The SmartSpice VZERO=2 option is not supported for IBIS buffers
     
  • Unlike other simulators, the IBIS Golden Parser is not incorporated into SmartSpice yet. As a consequence SmartSpice does not check the syntax of .ibs files and just issues a generic ‘parse error’ message if the syntax of an .ibs file is not in compliance with IBIS v3.2 specifications. To avoid such problems all .ibs files should be systematically verified with the Golden Parser, freely available as an executable on the IBIS Open Forum web site. If the Golden Parser reports warnings and errors, the .ibs file can probably not be used in SmartSpice netlists
     
  • SmartSpice buffers correspond to IBIS [Model] descriptions in .ibs files and so do not account for packages, which are defined in [Component] descriptions. However it is possible to add manually equivalent networks in the netlist (made of passive devices R_pkg, C_pkg and L_pkg whose values are taken from .ibs files)
     
  • The series, series switch and terminator buffers are not supported in this beta-release. They are currently being implemented
     
  • The capability for SmartSpice to use [Component] descriptions is also under development

 

References

  1. Peivand F. Tchrani, Yuzhe Chen, Jiayuan Fang, “Extraction of transient behavioral model of digital I/O buffers from IBIS”, 46th IEEE Electronic Components&Technology Conference, Orlando, May 28-31, 1996, pp 1009-1015
  2. Ying Wang, Han Ngee Tan, “The development of analog SPICE behavioral model based on IBIS model”, Ninth Great Lakes Symposium on VLSI, pp.101-104, 1999

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