The Importance of Mesh Definition in Strained-Si Heterostructure Simulation

Introduction

Computer simulation is used extensively to verify physical phenomena in semiconductor devices. Meshing plays an essential role in obtaining good simulation results. If care is not properly taken, serious errors may occur in the results. The objective of this article is to identify errors in the simulation of the strained-Si heterostructure MOSFET device using ATLAS, Silvaco’s two-dimensional numerical simulator.

 

Simulation Structure

Many research groups have extensively investigated Si/SiGe heterostructure MOSFETs in recent years [1, 2]. In these structures, a Si channel is grown under tensile strain between relaxed SiGe layers. The strain induced conduction band offset at the Si/SiGe heterointerface leads to the formation of a two-dimensional electron gas in the strained Si layer that substantially enhances electron mobility in bulk silicon. Si/SiGe heterostructure MOSFETs therefore deomonsterate excellent device performance.

The strained-Si p-channel heterostructure MOSFET is modeled for this article with ATLAS, Silvaco’s the two-dimensional numerical simulator, in order to study the effect of meshing on the simulation results, shown in Figure 1.


Figure 1. Strained-Si N-Channel Heterostructure MOSFET.

 

The structure consists of a 0.5µm strained-Si p-MOSFET. A thin strained graded Si1-xGex (110Å) buffer cap is sandwiched between the strained-Si layer (70Å) and relaxed Si1-xGex layer (0.402µm). This helps the user avoid the problem of hole confinement at the strained-Si/SiGe interface as the Ge grading reduces valence band discontinuity (Figure 2).


Figure 2. Zoom-in of Figure 1.

 

 

Discussion

The user must carefully define the strained-Si MOSFET structure, which has a dramatic effect on simulation results. It’s important to ensure that mesh nodes are both available for the defined regions and that fine meshes at regions where carrier activities are prominent, such as at junctions, the n-strained Si, n-strained Si1-xGex, and so on. If mesh nodes are not available at the defined regions, then the closest are chosen instead (Figure 3).


Figure 3. Poor definition of mesh nodes
at Strained/Relaxed Si1-xGex interface.

 

The interface between the Strained Si1-xGex and the Relaxed Si1-xGex in Figure 2 is defined at a depth of 0.01µm. If the meshes are defined so that nodes are unavailable in the region shown in Figure 3, then the interface between the Strained Si1-xGex and the Relaxed Si1-xGex forms a zig-zag pattern.

An incorrect simulation that results from poor mesh definition is illustrated in Figure 4. The vertical interface between the n+ polysilicon and SiO2 is located at x = 1.1µm (Figure 2). If mesh nodes are not available at x = 1.1µm, then the mesh appears as shown in Figure 4.


Figure 4. Poor mesh definition at vertical interface
between the n+ polysilicon and Silicon Dioxide.

 

The formation of the zigzag layer appears in Figure 4 at the interface x = 1.1µm. Some parts of the n+ polysilicon region are not defined as an electrode, even though the REGION and the ELECTRODE statements are both defined as the same region:

region num=11 material=poly x.min=0.6 x.max=1.1 y.min=-0.1 y.max=-0.003
elec num=2 name=gate x.min=0.6 x.max=1.1 y.min=-0.1 y.max=-0.003

This is because there is no mesh node is available at x = 1.1µm. As a result, ATLAS believes both the node at x = 1.11µm is the x.max for the REGION statement and the node at x = 1.08µm is the x.max for the ELECTRODE statement. This poor definition of the mesh at the vertical interface between the n+ polysilicon and SiO2 results in the inaccurate simulation of the devices shown in Figure 4.

The structure in Figure 4 is simulated by holding the drain bias at 0.1V and then ramping the gate voltage to 1.5V. Figure 5 is a plot of the simulated structure’s current flow and shows current flowing through the isolation oxide which is incorrect.


Figure 5. Poor mesh definition which results in
current flowing through the isolation oxide.

 

Figure 6 shows the simulated current flow lines with proper mesh definition at both the interface between the strained Si1-xGex and the relaxed Si1-xGex, and the vertical interface between the n+ polysilicon and SiO2. All the current flow lines are confined within the semiconductor region.


Figure 6. With proper mesh definition, the current flowlines
are confined within the semiconductor region.

 

Summary

To conclude, careful meshing is extremely important to device simulation. Simulation software users must carefully allocate mesh nodes at the defined regions as well as define fine meshes at regions of high activity.

 

References

  1. G. A. Armstrong and Chinmay K. Maiti, "Strained-Si Channel Heterojunction p-MOSFETs", Solid-State Electronics, Volume 42, Issue 4, April 1998, Pages 487-498
  2. P. A. Clifton, S. J. Lavelle and A. G. O'Neill, "Sub-micron Strained Si:SiGe Heterostructure MOSFETs", Microelectronics Journal, Volume 28, Issues 6-7, 9 August 1997, Pages 691-701

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