Schematic Driven Layout

Introduction

Expert schematic driven layout (SDL) is a CAD tool which increases the productivity of layout design by automating cell generation and providing visual cues to assist the wiring process. In the current implementation, schematic driven layout is used to automatically create IC layouts based on information from a netlist. Cell instances are created from existing cells. P-cells are instanced with parameters from the netlist file. Schematic driven layout automatically transfers net names, instance names and connectivity information from netlist to the layout. Automatic instantiation of cells with built-in connectivity support dramatically speeds up layout designer’s productivity and accuracy.

 

Operation Flow

Expert schematic driven layout operation flow is depicted in Figure 1.

Figure 1. Expert schematic driven layout operation flow

 

Preparing for Schematic Driven Layout

An existing ELD project file must be opened for the automatically generated cells to be placed. Use the ‘Tools>>SDL>>Load Netlist’ menu command is used to load the file with the netlist. Circuit information will be displayed in the netlist panel with the circuit hierarchical tree (Figure 2). To run Schematic driven layout a library of predefined standard cells (resistors, capacitors, transistors, diodes, and other finished devices) must be placed in your custom cell. These standard cells can be located either in the current project or in the activated cell library. Cell libraries can be activated by ‘Libraries>>Library setup’ dialog panel. If the name of a standard cell differs from the name of the corresponding netlist instance, you have to provide a mapping file with correspondences between names. Each line of the mapping file should contain the subcircuit name and the layout cell name separated by a space or tab character:

AND2 and2

MUX4 LIB1::MUX_4

Note that the library name for a cell from a library should be included in the cell name (‘LIB1::MUX4’ means cell MUX4 from library LIB1).

 

Figure 2. Netlist panel.

 

 

Initial Placement

Go to the circuit hierarchy tree in the netlist panel. Position your cursor at the location of the subcircuit you want to lay out and click the right mouse button. Select ‘Create’ command in the popup menu. Automatic cell generation will be performed. Cell area is computed from the areas of the individual components plus the area required for wiring. If an individual component has already been laid out, the actual area is used. If no layout exists, the area of a component is estimated from component parameters. The position of the devices will be calculated automatically to fill out the estimated cell area. The cell view window displays the geometry of the created layout (Figure 3).

If the selected subcircuit is hierarchical and the underlying instances not calculated yet, they will be laid out as well.

Figure 3. Initial placement with highlighted nets.

 

 

Layout Editing

Once the automatic placement is finished editing we can be started. Expert features a user-friendly interface for editing the generated design layout. Electrical connectivity is highlighted (Figure 3) to simplify design wiring. Expert shows “flight lines” to indicate which pins belong to the same net and should be connected to each other. The flight lines are redrawn automatically during layout editing.

There are several ways to do wire routing in your design. Expert ‘Wiring’ tool may be used to automatically place a wire connection between selected contacts. Pins can be connected manually by a wire object. To perform wire routing user’s should choose a wire tool in the Expert design bar and then simply click at each point at which the connection should be. Other parameters (e.g. layer, thickness, wire joint and end styles) for how the wire should be drawn may also be specified. Expert multiwire tool is used to create interconnects between pins using wire segments lying in different layers and connected by special contact cells. Any other primitive layout object to make connection between pins may also be used.

Expert submenu ‘Tools>>SDL’ contains many useful commands and options to simplify cell routing. The following list contains helpful hints for interconnect operations:

  • Use ‘Tools>>SDL>>Update Connectivity’ command and ‘Tools>>SDL>>Show unfinished Nets only’ option to check nets which are not connected yet (Figure 4)
     
  • ‘Tools>>SDL>>Show Global Nets’ option is used to hide or show Global nets. Global nets have a lot of connections (Figure 5), therefore turning its visibility off decreases the congestion of flight lines and simplifies design editing
     
  • Dialog panel ‘Tools>>SDL>>Nets Bar’ is used to choose flight line style and select nets for which flight lines are to be shown (Figure 6)
     
  • ‘Tools>>SDL>>Show Ports’ option is to show pin geometry inside a cell instance. This is useful when design is being edited in the ‘lazy’ instance view mod
     
  • Check option ‘Tools>>SDL>>Show Shorted Nets Only’ to show which nets overlap (Figure 7)

 

Figure 4. Highlighting the unfinished nets only.

 


Figure 5. All nets are highlighted.

 

Figure 6. Net Bar panel for managing of connectivity drawing.

 

Figure 7. Highlighting of shorted nets only.

 


Conclusion

We have described the first phase of development of Expert schematic driven layout.
In the future, Expert schematic driven layout tool will use circuit description from Silvaco’s Scholar schematic editor. It will provide the initial positions for the generated layouts to resemble the placement of the schematic instances.

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