Temperature Effects in SmartSpice LEVEL=6
Ferroelectric Capacitance Model
From Ramtron International Corporation

 

Introduction

Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of SILVACO Simulation Standard. This model utilizes a new concept of double distribution of domain reversal voltages. The temperature effects were not detailed in the previous article. This application note discusses the implementation of the temperature effects and updates the device syntax.

 

Features

The updated ferroelectric model is invoked in SmartSpice by setting LEVEL=6 in the capacitance model card. This model differs from its predecessor (model FCAP LEVEL=5) in that the ferroelectric capacitor is regarded as a non-linear capacitor with Polarization-Voltage (P-V) hysteresis loop, however the biases in the ferroelectric materials are reversed at reversal voltages with double distributions. As compared with the LEVEL=5 model, the LEVEL=6 model demonstrates the following improvements: more accurate simulations of ferroelectric hysteresis loops and sub-loops, improved voltage pulse responses, faster simulation speed (up to six times faster), and added temperature dependence.

 

Ferroelectric Capacitor Element

SmartSpice device statement syntax:

Note: Device syntax is updated from that published in the April 2002 Simulation Standard

Cxxx n1 n2 mname <V0=val> <P0=val> <A=val>

Cxxx: Capacitor element name; must begin with "C."
n1, n2: Positive and negative terminal node names, respectively.
mname: Model name (must be ferroelectric capacitor model).
V0: Initial voltage across the ferroelectric capacitor (V). Default is 0.0.
P0: Initial polarization (mC/cm2) from positive node (n1) to negative node (n2). Default is 0.0.
A (AREA): Capacitor area (m2). Default is 1.0E-12.

One difference to note is that the LEVEL=5 ferroelectric capacitor uses the unit-less parameter, IP, for initial polarization while the LEVEL=6 ferroelectric capacitor uses the initial polarization parameter, P0, in µC/cm2. The input for the capacitor size in the LEVEL=6 model is the capacitor area, and can be specified using either A or AREA in m2.

 

Temperature Effects in LEVEL=6 Ferroelectric Capacitance Model

SmartSpice model syntax:

.MODEL mname C LEVEL=6 <parameter=value> …

mname: Model name.
C: Specifies capacitance model.
LEVEL=6: FRMC model.
parameter: Any model parameter name.

 

The model parameters were documented in the April 2002 Simulation Standard article with the exception of the temperature parameters. Table 1 shows a complete list of the model parameters including the updated default parameter values as well as the temperature coefficient parameters.

LEVEL=6 FERROELECTRIC CAPACITOR MODEL PARAMETERS
Parameter Description Units Default
VMAX Maximum voltage V 3.898e+00
PMAX Maximum polarization at VMAX µC/cm2 3.787e+01
KPMAX 1st order temperature coefficient of PMAX   -8.803e-03
K2PMAX 2nd order temperature coefficient of PMAX V -8.616e-05
VSAT Saturated model point V 2.452e+00
VCR Minimum voltage for domain switching   4.903e-01
AS1 Curve fitting parameter   1.348e+00
BS1 Curve fitting parameter   1.174e+00
CS1 Curve fitting parameter   1.634e+00
AS2 Curve fitting parameter   -1.085e+00
BS2 Curve fitting parameter   1.444e+00
CS2 Curve fitting parameter   1.859e+00
DS0 Curve fitting parameter   5.513e-01
AU1 Curve fitting parameter   1.457e+00
BU1 Curve fitting parameter   1.432e+00
CU1 Curve fitting parameter   1.377e+00
AU2 Curve fitting parameter   -1.109e+00
BU2 Curve fitting parameter   1.820e+00
CU2 Curve fitting parameter   1.574e+00
DU0 Curve fitting parameter   5.695e-01
LEVEL=6 FERROELECTRIC CAPACITOR MODEL PARAMETERS:
Temperature Coefficients
KAS1 1st order temperature coefficient of AS1   -3.178e-03
KBS1 1st order temperature coefficient of BS1   -1.970e-03
KCS1 1st order temperature coefficient of CS1   -4.562e-03
KAS2 1st order temperature coefficient of AS2   3.074e-03
KBS2 1st order temperature coefficient of BS2   -2.539e-03
KCS2 1st order temperature coefficient of CS2   -4.343e-03
KDS0 1st order temperature coefficient of DS0   -1.869e-04
KAU1 1st order temperature coefficient of AU1   -4.090e-03
KBU1 1st order temperature coefficient of BU1   -2.641e-03
KCU1 1st order temperature coefficient of CU1   -4.944e-03
KAU2 1st order temperature coefficient of AU2   4.495e-03
KBU2 1st order temperature coefficient of BU2   -4.626e-03
KCU2 1st order temperature coefficient of CU2   -4.637e-03
KDU0 1st order temperature coefficient of DU0   -4.621e-04
K2AS1 2nd order temperature coefficient of AS1   3.423e-05
K2BS1 2nd order temperature coefficient of BS1   -3.860e-06
K2CS1 2nd order temperature coefficient of CS1   2.176e-05
K2AS2 2nd order temperature coefficient of AS2   -3.725e-05
K2BS2 2nd order temperature coefficient of BS2   -8.596e-06
K2CS2 2nd order temperature coefficient of CS2   1.689e-05
K2DS0 2nd order temperature coefficient of DS0   1.575e-06
K2AU1 2nd order temperature coefficient of AU1   4.337e-05
K2BU1 2nd order temperature coefficient of BU1   -4.328e-06
K2CU1 2nd order temperature coefficient of CU1   1.882e-05
K2AU2 2nd order temperature coefficient of AU2   -5.218e-05
K2BU2 2nd order temperature coefficient of BU2   -4.039e-06
K2CU2 2nd order temperature coefficient of CU2   1.254e-05
K2DU0 2nd order temperature coefficient of DU0   2.099e-06

Table 1. Complete list of the model parameters including the updated default
parameter values as well as the temperature coefficient parameters.
NOTE: All blank cells indicate a number with no units.

 

Simulation Results

The improved accuracy of the LEVEL=6 model compared to the LEVEL=5 model was documented in the April 2002 Simulation Standard article. Here we show comparison of the simulated vs. measured results at three different temperatures to validate the temperature modeling. The test circuit used is shown in Figure 1.


Figure 1. Test circuit for ferroelectric capacitor
simulations. (Sawyer-Tower circuit)

 

Temperature effects for the ferroelectric capacitor model are calculated in the following form for all model parameters:

AS1eff = AS1 + KAS1 * (TEMP – TNOM) +
K2AS1 * (TEMP – TNOM)2

Figures 2, 3, and 4 show measured and simulated hysteresis loops at 3V and 5V, for temperatures of 27?C, 60?C, and 90?C, respectively. The input stimulus for these results was a sinusoidal voltage waveform at 10 KHz. This shows very close agreement between simulation and measurement at temperature.


Figure 2. Measured (red) and simulated (blue) hysteresis loops at 27?C.
[Courtesy of Ramtron International Corporation]

 


Figure 3. Measured (red) and simulated (blue) hysteresis loops at 60?C.
[Courtesy of Ramtron International Corporation]

 


Figure 4. Measured (red) and simulated (blue) hysteresis loops at 90?C.
[Courtesy of Ramtron International Corporation]

 

Conclusions

The new ferroelectric capacitor model implemented in SmartSpice as LEVEL=6, has been shown to accurately simulate hysteresis loops at various temperatures. This model based on double distributions of domain reversal voltages has shown advantages over the LEVEL=5 model as described in the April 2002 Simulation Standard article. In this article, we have presented details of the implementation of temperature effects, comparison of simulation results to measured data, and updated the device syntax.

SILVACO gratefully acknowledges Ramtron International Corporation for the development of the ferroelectric capacitance model and the data presented here.

References

  1. "Polarization Reversal Kinetics in Ferroelectric Liquid Crystals", Proceedings of the Sixth International Meeting on Ferroelectricity, Kobe 1985, Yoshihiro Ishibashi, Japanese Journal of Applied Physics,vol. 24 Suppl. 24-2, 126 (1985)
  2. Simulation Standard Volume 12, Silvaco International, April 2002
  3. ATLAS Users Manual, Silvaco International. December 2002.

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