New Berkeley BSIM4v2.1 MOSFET Model
Available Within SmartSpice/UTMOST III

1. Introduction

So far the BSIM3v3.2 MOSFET model, developed by UC-Berkeley, has been considered as the industry standard model for deep-submicron CMOS design. It was rapidly adopted by IC companies and foundries for modeling devices down to 0.25 . However, for device scale down to 0.10 , some physical mechanisms need to be better characterized.

BSIM4 model is developed to explicitly address the following issues, for which BSIM3v3 was found lacking and inaccurate:

  • Modeling of sub-0.13 microns MOSFET devices
  • High-frequency analog and high-speed digital CMOS circuit simulation
  • Layout-dependent parasitics model

UC-Berkeley officially released BSIM4v0.0 for the first time on March 24, 2000. Later versions BSIM4v1.0, BSIM4v2.0 and BSIM4v2.1 were released on October 11, 2000, on April, 06 2001 and on October 05, 2001, respectively. They account for user's feedback and provide bug fixes over earlier versions.

This article is intended to give an overview of the implementation of BSIM4 within Silvaco products. Further details and up-to-date information may be found in SmartSpice/UTMOST Modeling Manuals and SmartSpice Release Notes.

Readers interested in obtaining more details about BSIM4 may refer to the Berkeley documentation and source code, available for download at: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html


2. Fundamental Improvements Over BSIM3v3.2

Like BSIM3v3.2, BSIM4 accounts for major physical effects:

  • Short/Narrow channel effects on threshold voltage
  • Non-uniform doping effects
  • Mobility reduction due to vertical field
  • Channel length modulation (CLM)
  • Source/Drain parasitic resistances
  • Substrate current induced body effect (SCBE)
  • Quantum mechanic charge thickness model
  • Unified flicker noise model

BSIM4 has the following major improvements and additions over BSIM3v3.2:

  • an accurate new model of the intrinsic input resistance for both RF, high-frequency analog and high-speed digital applications
  • flexible substrate resistance network for RF modeling
  • a new accurate channel thermal noise model and a noise partition model for the induced gate noise
  • a non-quasi-static (NQS) model that is consistent with the Rg-based RF model and a consistent AC model that accounts for the NQS effect in both transconductances and capacitances
  • an accurate gate direct tunneling model
  • a comprehensive and versatile geometry-dependent parasitics model for various source/drain connections and multi-finger devices
  • improved model for steep vertical retrograde doping profiles
  • better model for pocket-implanted devices in Vth, bulk charge effect model, and Rout
  • asymmetrical and bias-dependent source/drain resistance, either internal or external to the intrinsic MOSFET at the user's discretion
  • acceptance of either the electrical or physical gate oxide thickness as the model input at the user's choice in a physically accurate manner
  • the quantum mechanical charge-layer-thickness model for both IV and CV
  • a more accurate mobility model for predictive modeling
  • a gate-induced drain leakage (GIDL) current model, available in BSIM for the first time
  • an improved unified flicker (1/f) noise model, which is smooth over all bias regions and considers the bulk charge effect
  • different diode IV and CV characteristics for source and drain junctions
  • junction diode breakdown with or without current limiting
  • dielectric constant of the gate dielectric as a model parameter

 

3. Silvaco Implementation

The Silvaco implementation of BSIM4 is based on the official Berkeley releases. BSIM4 is currently accessible within SmartSpice/UTMOST by specifying the model selector LEVEL=14. The alias LEVEL=54 is also supported for HSpice compatibility.

The most recent version (BSIM4v2.1) is selected by default but older versions may be invoked by specifying the model parameter VERSION=0.0, 1.0 or 2.0. In the Silvaco implementation, VERSION is a real value and not a string, as in the Berkeley code. Consequently, the Berkeley syntax VERSION=4.2.1 corresponds to VERSION=2.1 in SmartSpice/UTMOST III. A warning message is issued when an invalid VERSION number is given. It is recommended to systematically use the most recent version to benefit from the last Berkeley bug fixes and improvements.

The structure of the original Berkeley code has been modified. These changes do not directly involve equations, except minor bug fixes in derivatives. So they do not affect the accuracy of results but may significantly improve convergence. The Silvaco implementation offers the best performances regarding speed and convergence without any loss of accuracy.


3.1 Differences Between BSIM4v2.1 and BSIM4v2.0
BSIM4v2.1 provides bug fixes over its previous version, BSIM4v2.0. Most of them were already included in the Silvaco implementation of BSIM4v2.0 when UC-Berkeley released the new version. Consequently, only the changes listed below have been incorporated. They are active only if VERSION=2.1 is selected:

  • Gate Induced Source Leakage (GISL) is added to give an enormous improvement in simulation convergence. Together with GIDL, it makes the gate induced leakage component of the substrate current symmetric

  • The warning limits for effective channel length, channel width and gate oxide thickness (Leff, LeffCV, Weff, WeffCV, Toxe, Toxp and Toxm) are substantially decreased to avoid a large number of warnings when BSIM4 is used beyond its design region. For meaningful results, it is still recommended to keep these variables/ parameters within the BSIM4 design region. This change is intended only to allow users to extend the model beyond this region with fewer warnings

  • The model parameter ACDE is now checked only when CAPMOD=3 to avoid useless warning messages

  • The 1/f noise bug fix avoids negative DelClm when calculating noise density by turning off the second part of the noise density equation

  • In addition, this version adds many variables as output such as some of the current components (igs, igd, igb, igcs, igcd, isub, igidl, igisl) to ease the model verifications

3.2 Differences Between BSIM4v2.0 and BSIM4v1.0
The improvements incorporated into BSIM4v2.0 are bug fixes and two new model parameters XL and XW.

XL and XW are geometry offset parameters due to mask/etch effect with default values of 0.0. With these changes, the BSIM3 parasitic resistance model file becomes a compatible subset of the BSIM4 parasitic resistance model.

In versions 0.0 and 1.0, the value of the intrinsic capacitance cbdb of the CAPMOD=0 capacitance model was wrong. This has been corrected in version 2.0.

Also, the computation efficiency is enhanced due to a better extraneous node allocation strategy. In version 2.0, internal drain and source nodes are created only if access resistances have non-zero values or if a noise analysis is performed with the holistic thermal noise model selected (TNOIMOD=1). When extraneous nodes collapse, the size of the matrix is reduced, leading to a significant gain of speed, especially with large circuits.

3.3 Differences between BSIM4v1.0 and BSIM4v0.0
The improvements of BSIM4.1.0 over BSIM4.0.0 are bug fixes and an analytical equation for the model parameter PIGCD when it is not specified. The relevant changes are:

  • Gate Tunneling Currents: in BSIM4.0.0, PIGCD is set to a constant value (1.0) if unspecified. In BSIM4.1.0, its default value is given by an analytical equation:

    where B is a constant, set to 7.45669e11 for NMOS or to 1.16645e12 for PMOS, and TOXE is a model parameter (Electrical gate equivalent oxide thickness).

  • Thermal Noise Charge Based Model (TNOIMOD=0): in BSIM4.0.0, the inversion charge Qinv used in the thermal noise current formulation depends on the effective saturation voltage calculated for the drain current equation, which causes a current spike. In BSIM4.1.0, this bug has been fixed by replacing the original value of Vdsat by a simple expression, corresponding to a long-channel saturation voltage:

  • Parameter checking: in BSIM4.0.0, the maximum number of device fingers (NF) is limited to 500. In BSIM4.1.0, this limit is removed and if NF is too large and makes the effective width (Weff) to be lower than or equal to zero, a fatal error will be issued

 

3.4 Silvaco Specific Features
The following SmartSpice-specific features have been added to the original Berkeley implementation, for all BSIM4 versions:

  • The BSIM4 code has been optimized to benefit from SmartSpice multi-threading capabilities. A gain of speed of 30% or more may be observed on 2-processors machines, especially when running large circuits

  • The VZERO and BYPASS options are fully supported. Specifying VZERO=2 and/or BYPASS=1 on .OPTION lines may significantly speed-up computation for transient analysis. The original Berkeley BYPASS criterion has been modified to ensure accuracy and for HSpice compatibility

  • The SmartSpice standard multiplier, useful to put several identical transistors in parallel, is supported as a BSIM4 instance parameter M. This parameter is not equivalent to the instance parameter NF (number of fingers) introduced in BSIM4 by Berkeley to account for devices in parallel. Please refer to Berkeley documentation for further details on this new parameter

  • In SmartSpice, it is possible to specify the temperature of each device using the standard instance parameters TEMP and DTEMP. They are also supported for BSIM4 instances. TEMP has the highest priority and correspond to the temperature of the device in. If TEMP is unspecified and DTEMP is specified, the instance temperature is evaluated by adding DTEMP to the circuit temperature. If none of these parameters are specified the circuit temperature is used, which defaults to 27 if unspecified with .OPTION or .TEMP statements

  • The original Berkeley BSIM4 parameter checking scheme has been modified to avoid the same warning message be issued several times when a parameter is out of range. In the Silvaco implementation, instance and model parameters are separately tested. As the main consequence, each warning message is now issued only once

  • The implementation of NQS models has been optimized so that related matrix elements are created only when TRNQSMOD or ACNQSMOD selector are set to 1. That fixes a singular matrix error when TRNQSMOD=1 and ACNQSMOD=0

  • The SmartSpice standard conductances GMIN/ DCGMIN have been added. They are connected in parallel with bulk junction diodes and between internal drain and source nodes. They account for the instance multiplier (M) and the number of device fingers (NF)

  • The CAPTAB and DCCAP options are supported

  • The terminal currents and charges can be printed, plotted or saved for DC, TRAN and AC analysis using the SmartSpice syntax @instance_name[variable_name]. The related variable names are listed in Table 1

 

Variable name (alias) Definition
id (cd) Drain terminal current
cs Source terminal current
cg Gate terminal current
cb Bulk terminal current
*qdrain Intrinsic drain charge
*qbulk Intrinsic bulk charge
*qgate Intrinsic gate charge
*qd Total drain charge
*qb Total bulk charge
*qg Total gate charge
*cqd Total drain capacitance current
*cqb Total bulk capacitance current
*cqg Total gate capacitance current

Table 1. BSIM4 extra output variables added in SmartSpice.

 

The variables marked with an asterisk are systematically computed after transient and small-signal analysis. For DC analysis, they are computed only if DCCAP option is turned on.


Figure 1. BSIM4 DC characteristics.

 


Figure 2. BSIM4 RF/High-Speed model: digital ring oscillator.