Verilog-A Release in SmartSpice

 

1. Introduction

We give in this article an introduction to the Verilog-A SmartSpice interface. This new feature in SmartSpice allows the user to write their own physical models in the Verilog-A language. The first section of the paper gives a brief overview of the Verilog-A language. The second presents the ease of use of simulating transistor models as well as digital circuits with the new Verilog-A SmartSpice interface.

2. The Verilog-A Language

Verilog-A belongs to the Analog Hardware Description Language (AHDL) class of computer languages. These AHDLs are now widely used to help design analog systems, with high level behavioral forms for continuous systems.

Verilog-A is a subset of Verilog-AMS (Analog Mixed Signal), a standard defined by Open Verilog International (OVI) as an extension of the IEEE 1364 Verilog HDL standard (Verilog Digital) [1]. The Verilog-A supported by SmartSpice is the latest version 2.0 defined in March 2000. Two kinds of description are possible in Verilog-A, structural description and behavioral description.

2.1. Structural Description

The structural description used in Verilog-A is similar to the one available in Digital Verilog. The basic component is a "module". A module has an interface consisting of ports and parameters. Inside a module, other modules can be instantiated. The syntax to instantiate a module is as follows:

<module_name> #(<parameter_values>)
<name_of_the_instance> (<connection_list>)

Listing 1 shows a structural description of a RLC circuit. In the first instantiation statement of Listing 1, resistor is the module name, the value 200 is assigned to the first parameter, r1 is the instance name and in and tmp are the ports associated to the resistor module ports.

 

module rlc(in, out, gnd);

input in, gnd;

output out;

electrical in, out, gnd;

electrical tmp;

resistor #(200) r1 (in, tmp);

inductor #(125) l1 (tmp, out);

capacitor #(1u) c1 (out, gnd);

endmodule;

Listing 1. Verilog-A structural RLC circuit.

 

2.2. Analog Behavioral Description

In Digital Verilog, the behavioral description uses blocks, integer variables and bit signals. With Verilog-A, the behavioral description uses analog block, integer and real variables and analog signals. An analog signal is declared following a discipline. A discipline is an abstract data type that describes a continuous domain by associating a potential and a flow nature. To assign an expression to a signal, Verilog-A introduces the contribution operator <+. It is used in a contribution statement where a behavior relation is described between input and output signal.

output_signal <+ f(input_signal);

Listing 2 shows a capacitor module. The node n1 and n2 are declared as inout ports and with electrical discipline. The current of the branch between n1 and n2 is assigned the value returned by the function ddt(). The ddt() function is a Verilog-A built-in analog function that returns the time derivative value of an expression.

module capacitor (n1, n2);

inout n1, n2;

electrical n1, n2;

// node n1 and n2 declared with the electrical discipline parameter real c=1p;

// default value is 1p analog begin i(n1,n2) <+ ddt(c*V(n1,n2));

end endmodule


Listing 2. Verilog-A capacitor model.

2.3 Multi-Discipline Description

The Verilog-A language can support the description of systems used in many disciplines such as electrical, mechanical, fluid dynamics and thermodynamics. For this purpose, the language provides a Standard Definitions file where the main disciplines are defined. Table 1 shows all available discipline with their associated natures. In the same module, nodes from different disciplines can be mixed.

discipline potential
nature
flow
nature
potential access flow access
electrical Voltage Current V I
magnetic Magneto_Motive_Force Flux MMF Phi
thermal Temperature Power Temp Pwr
kinematic Position Force Pos F
rotational Angle Angular_Force Theta Tau

Table 1. Predefined disciplines in the standard definition Verilog-A file.

 

3. Verilog-A Examples Using SmartSpice

We present in this section some examples simulated with the latest SmartSpice Verilog-A interface.

3.1 A Bipolar Transistor with Thermal Effects

The following Verilog-A model describes a bipolar transistor with thermal effects. The model has been derived from a VHDL-AMS model from the University of Southampton [2]. The description uses the standard Ebers-Moll equations. A set of heat flow equations have been connected to an output node declared with a thermal discipline. Listing 3 shows some of the Verilog-A heat flow equations. This example shows the ease of mixing nodes from different disciplines in the same design. The nodes base, collector, and emitter are electrical. The node thermalTerminal is thermal.

// collector junction equation (assignment target is a quantity)

I(base,collector) <+ Ise/Bre*exp(V(base,collector)/(Nr*Vth));

// emitter junction equation

I(base,emitter) <+ Ise/Bfe*exp(V(base,emitter)/(Nf*Vth));

// transport current equation

I(collector,emitter) <+ I(base,emitter)*Bfe - I(base,collector)*Bre;

// heat flow equations

Pwr(ThermalTerminal) <+ Temp(ThermalTerminal) * CoolingConductance;

// power flow

Pwr(ThermalTerminal) <+ - abs(I(collector,emitter) * (V(base,collector)-V(base,emitter)));

// heat storage rate due to thermal inertia:

Pwr(ThermalTerminal) <+ HeatCapacity*ddt(Temp(ThermalTerminal));

Listing 3. Verilog-A code for some equations of the bipolar transistor with thermal effects

In Figure 1, a transient was applied to the base contact and the transistor temperature was observed to vary as shown in Figure 1 (bottom chart).


Figure 1. Temperature effects for the Verilog-A BJT model.

 

3.2 VBIC SmartSpice Verilog-A Comparison

The Vertical Bipolar Inter-Company (VBIC) model is a bipolar transistor model available with SmartSpice by selecting LEVEL=5 for a BJT device. The Verilog-A implementation intends to represent most of the same model effects. Macros exists in the code to select the number of terminals (with or without the substrate node, with or without a thermal node), the thermal network and the excess phase network. The Verilog-A model shows that a complex model can be simulated easily with SmartSpice and have the same level of accuracy. The Verilog-A code is 883 lines long, contains 108 parameters and 7 internal nodes to represent the intrinsic and extrinsic contributions. Figure 2 shows a DC analysis simulation with SmartSpice and the Verilog-A models. Results with both models are close enough that we can not distinguish one curve from the other.


Figure 2. Ic vs Vc characteristics of the VBIC models
within SmartSpice and from using Verilog-A.

 

3.3 A Modulus 10 Divider

With Verilog-A, it is also possible to describe digital components at a behavioral level. We show in this section a digital circuit where the basic components (the RS flipflop and the OR gate) are Verilog-A modules. There are four RS flipflop instances and one OR gate. Figure 3 shows the schematic of the circuit and Figure 4 shows the output voltage in response to the input voltage.


Figure 3. Schematic of the Mod-10 divider

 


Figure 4. Input and Output Voltage for the mod-10 divider in Verilog-A

 

4. Conclusion

We provided in this article an introduction to the SmartSpice Verilog-A interface. We have shown that the user can developed very easily their own analog model as well as digital components. Furthermore, models defined with Verilog-A can be as complex as internal SPICE models and give the same level of accuracy.

References

  1. Verilog-AMS Language Reference Manual, Analog & Mixed-Signal Extensions to Verilog HDL, Version 2.0, February 18, 2000, Open Verilog International.
  2. Southampton VHDL-AMS Validation Suite, www.syssim.ecs.soton.ac.uk