Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D

Introduction

This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite. The double-gate MOSFET is one of the most attractive alternative to classical MOSFET structure for gate length down to 20nm. The main advantage of the FinFET is the ability to drastically reduce the short channel effect. In spite of his double-gate structure, the FinFET is closed to its root, the conventional MOSFET in layout and fabrication. 3-D numerical simulations of the FinFET are performed in this article, in order to validate the basic principles and to uncover several important aspects: evaluation of the length , width and quantum effects.

 

Device Features

The features of the structure are shown in Figure 1 are: (1) a transistor is formed in a vertical ultra –thin Si fin and is controlled by a double-gate, which considerably reduced short channel effects; (2) the two gates are self aligned and are aligned to S/D; (3) S/D is raised to reduce the access resistance; (4) Up to date gate process: low temperature, high -k dielectrics can be used and (5) the structure is quasi-planar because Si Fin is relatively short [1,2].

 

Figure 1. FinFET layout design and device structure. The bottom is A-A cross section and the right is B-B cross section.

 

Device Simulation

The 3-D SILVACO simulation suite including Device3D, DevEdit3D and TonyPlot3D, allows device engineers to study deep sub-micron devices which are 3-D by nature like the FinFET presented above. Furthermore, 3-D simulations give access to data impossible to measure like charge distribution, potential, electric field and current lines.

A 3-D FinFET structure was designed by using DevEdit3D. This is an advanced tool for structure editing and mesh generation. The device structure was realized by drawing first the FinFET, from the bottom view (Figure 2),in a (x,y) plane before extending it in the z-direction.

Figure 2: Illustration of DEVEDIT3D used to build the FinFET structure

 

The z-direction in this case corresponds to the vertical to the substrate. The final 3-D structure is shown in TonyPlot3D (Figure 3).

Figure 3: Plot of a 50-nm FinFET 3-D structure for a width of 50nm

 

The basic characteristics of this Finfet was Tox=2nm length=50nm width=50nm and Fin height=50nm. Note that we have defined a parametrized structure for subsequent use in our automation tool which make much more easier any kind of variation (length, width ..) to perform large scale simulation.

The main physical effects (mobility, carrier statistics, recombination) were expressed by a set of models universally used for simulating the MOS technology: mobility dependence of the electric field and doping level, Boltzmann statistics and Schokley-Read-Hall generation recombination mechanisms[3].

 

Simulation Results

Typical I-V characteristics of a 50-nm gate length are shown in Figure 4. The leakage current caused by DIBL was well suppressed.

Figure 4: 50-nm FinFET IdVg curves for a width of 50nm.

 

 

The rool-off of a FinFET with a width of 50nm is well controlled as can be seen in Figure 5. This result can be correlated to the good control of the channel potential due to the double gate.

Figure 5: Threshold voltage as a function of gate length for a width of 50-nm.


The width of this FinFET is adjusted by the number of Si fins. Let say you want to double the width of your device then you have to put 2 Fins between source and drain (Figure 6).

Figure 6: Structure of a 2-parallel channel device. Gate length 50-nm.

 

Note that this can be achieved very simply using the "mirror" feature in DevEdit3D. The resulting I-V curve can be seen in Figure 7: drain current is doubled.

Figure 7: Drain current comparison between single and
2-parallel channel device. Gate length 50-nm.

 

Finally we have made simulations using our quantum module named Quantum3D. The result is plotted in Figure 8. One can see a shift in the threshold voltage indicating some quantum effect. This correction is quite small as indicated in [2].

Figure 8: Quantum effect in a 50-nm with a width of 50nm.

 

 

Conclusion

Sub 50-nm FinFETs were successfully simulated using 3-D SILVACO simulation tools. It is very easy to study the impact of the geometry and doping of this 3-D device using Device3D. Indeed more and more people take a look at this novel structure since it is an attractive successor to the single-gate MOSFET

 

References

  1. D.Hisamato et al. - IEDM'98
  2. X.Huang et al. - IEDM'99
  3. SILVACO International - ATLAS User’s Guide.