Scholar - SmartSpice Interface

One of the most useful features of the Scholar schematic capture is tight integration with the SmartSpice simulator. In effect, Scholar makes it possible to automatically generate SmartSpice netlist on the basis of the schematic. Such a possibility covers both analog and digital designs.

The main features of the interface are:

  • Scholar's library of symbols which makes it possible to generate netlist

  • mechanisms of creating a netlist which is oriented especially for the SmartSpice simulation process

Library of Symbols

Scholar's library of symbols consists of three major sets of elements.
  • Analog devices

  • Digital devices

  • Basic Scholar schematic symbols

The main advantage of Scholar's library is the complete set of elements that correspond to SmartSpice devices. They are the following:
  • Current sources - idc.body, cccs.body, cccspoly.body, cccspwl.body, ccs.body, ccvs.body, ccvspoly.body, ccvspwl.body;

  • Voltage sources - vccs.body, vccsbhv.body, vccspoly.body, vccspwl.body, vccstbl.body, vcs.body, vcvs.body, vcvsbhv.body, vcvspoly.body, vcvspwl.body, vcvstbl.body, vdc.body, vexp.body, vpl.body, vpulse.body, vpwl.body, vpwlfile.body, vpwlfiledesc.body, vpwlfiledesc2.body, vsffm.body, vsin.body,

  • Transistors - njfet.body, njfet4.body, njfet_b.body, nmes.body, nmes4.body, nmes_b.body, nmos.body, nmos4.body, nmos_b.body, npn.body, npn4.body, npn_b.body, pjfet.body, pjfet4.body, pjfet_b.body, pmos.body, pmos4.body, pmos_b.body, pnp.body, pnp4.body, pnp_b.body, l Other devices - cap.body, diode.body, ind.body, res.body, bcs.body, bvs.body, ltl.body, tline.body, txl.body;

Additionally, the library includes:
  • logical symbols - and2.body, inv.body, nand2.body, nor2.body, or2.body;

  • special schematic symbols - attributes.body, biflag.body, frame.body, frame_s.body, frame_b.body, gnd.body, gnd_2.body, inflag.body, outflag.body, pageflag.body, parameters.body, pwr.body.

All elements have clear graphical representations that are similar to those used in popular schematic capture tools. An example of a library element is shown in Figure 1.





Figure 1. Symbol of npn transistor.



Generation of Netlist Statements

The mechanism of the SmartSpice netlist generation is based on the use of Scholar's symbols' attributes.

As is described in [1] Scholar makes it possible to attach attributes to symbols. The attributes of the terminal library elements have the same names and meanings as corresponding components of SmartSpice statements.

The algorithm of the SmartSpice statement generation are embedded into a library element. It is based on the use of these attributes. In particular, the values of attributes are placed in SmartSpice statements. Therefore, in order to create a correct netlist a user need only to set the attribute values.

The resulting name of the element is formed using SmartSpice prefix, just as described in the SmartSpice User's Manual, and the original name is taken from the drawing.

Scholar provides the user with a number of possibilities concerning attribute modification. For example, a user can modify the values of attributes using Scholar Find/Modify dialog. An example of it is shown in Figure 2.





Figure 2 Find/Modify dialog.



A user has the ability to change not only the values of attributes, but also their visibility and placement on a drawing. It can be useful in order to make a drawing more clear and readable. According to the SmartSpice statement description some attributes are mandatory but others are optional. Scholar sets the values of mandatory attributes to "?". If the user forgets change the values of attributes Scholar will remember to set such values. It writes an error message to the session window during the checking drawing operation.

We just described the way that SmartSpice statements are created automatically. Another way is the use of the user defined statements attached to a symbol. Each element of the Scholar library has an additional attribute, named SPICE_STRING. It's value appears in the end of spice statement, if it is not empty. This attribute is reserved for special users' purposes. The main one is passing a user-defined statement into a netlist. It also can be used to add a comment at the end of a statement.

Let?s consider an example of library element.

The library has the number of elements that cover BJT devices. They all have the same SmartSpice statement, which is the following:


    Qxxx nc nb ne mname <area> <IC=vbe, vce> + <Temp=val> <M=val> <DTEMP=val>

Three of them (npn.body, npn4.body, npn_b.body) are n-p-n transistors, and another three elements (pnp.body, pnp4.body, pnp_b.body) are p-n-p transistors.

One of them is a n-p-n transistor that has three pins (shown on Figure 1). A second kind of transistor has four pins. One pin is a bulk node, which can be manually connected to any net on the drawing. Another kind of n-p-n transistor can be useful when a user wants to set the bulk node by default. There is Scholar's environment variable NBULK_NODE, which contains the name of the default net. During the writing of the netlist sets all such pins to the default bulk node for n-p-n transistors:


    set NBULK_NODE=GND


This is an example of setting default bulk node from the operating system shell, which the user can include in the Scholar configuration script.

The resulting SmartSpice string, for instance of npn_b transistor is the following:

QQ2 NET4 NET5 NET6 GND QNL 1.5 IC=0.6, 5.0

This transistor has the default bulk node, model with the name QNL, emitter area factor 1.5, and initial conditions are "vbe" 0.6 and "vce" 5.0.


Using Scholar-SmartSpice Interface

The process of using Scholar-SmartSpice interface consists of the following.

A user creates a schematic drawing of circuits and subcircuits, consisting of symbols of resistors, inductors, current and voltage sources, other semiconductor devices and other Scholar schematic symbols such as input/output flags, page connectors and so on. An example of the schematic is shown in Figure 3.





Figure 3. Example of Scholar Drawing



The resulting netlist for the circuit in Figure 3 is:

    **
    * Scholar Spice Netlist Generator
    **
    * Section name: SCHLR
    * Section timestamp: 16:34:24.00
    *
    * Structdef name: EX1
    *
    QQ2 NET4 NET5 NET6 QNL
    QQ1 NET3 NET2 NET6 QNL
    VVEE NET9 GND DC -12
    VVCC VDD GND DC 10
    CCLOAD NET3 NET4 5PF
    QQ3 NET6 NET7 NET9 QNL
    QQ4 NET7 NET7 NET9 QNL
    RRC1 VDD NET3 10K
    RRC2 VDD NET4 10K
    RRS1 NET1 NET2 1K
    RRS2 NET5 GND 1K
    RRBIAS VDD NET7 20K
    VVIN NET1 GND DC 0 SIN(0 0.1 5MEG ) AC 1
    * End of the netlist


Scholar-SmartSpice Interface provides the ability to operate Input Deck, which usually consist of three main parts:
  • Netlist;

  • Control statements;

  • Model descriptions;

Then the user modifies the values of attributes for devices. If a circuit is hierarchical, a user needs to create a generic wire list (gwl) file for all subcircuits in the design. Also the user needs to prepare a model and control file to finish the creation of the input deck for simulation. Then the user is ready to run SmartSpice, using menu command or the button on the Scholar toolbar.

Example of Input deck is the following:
    .include ex1.in
    .include ex1.mod
    .include ex1.ctrl
    .END


Also the user can only write a netlist file and use it in their own environment for their own purposes. It can be done from the "Write SmartSpice" Scholar menu command.



Reference
  1. Scholar: An Enhanced Multi-Platform Schematic Capture. Simulation Standard, Volume 10, Number 9, September 1999