Modeling and Parameter Extraction Technique for HV MOS Devices with BSIM3v3

 

Takao Myono, SANYO Electric Co., Ltd.

 

1. Introduction

We have developed several kinds of HV MOS devices whose device structures and doping levels in the offset regions differ depending on the specifications of the devices. We have developed the bi-directional HV MOS device (e.g., it can be used as a bi-directional MOS switch) with both drain and source offset regions, and we previously described its SPICE model [4] - [5] based on BSIM3v3 [1] - [3]. On the other hand, the uni-directional HV MOS device has only a drain offset region. That is, it does not have a source offset region with corresponding source resistance.

In this paper, I have used the same technique to model uni-directional HV MOS devices as previously reported for bi-directional HV MOS devices [4] -[5] while adopting a new parameter extraction technique. With the new uni-directional HV MOS modeling technique, the simulated I-V characteristics of the uni-directional n-channel HV MOS device match the measured characteristics well, which confirms its effectiveness.


Figure 1. Schematic structure of the uni-directional n-channel HV MOS device.

 

2. Uni-directional HV MOS Device Technology

Figure 1 shows the structure of our 45 V n-channel HV MOS device, with a gate-oxide film thickness (Tox) of 1350, channel length (L) of 3.2µm and offset of 3.2µm . A n-offset region of low doping concentration is used in the drain region, in order to realize high uni-directional drain-source breakdown voltage. Based on our device simulations, we consider that the basic operation of the bi-directional HV MOS device is as explained below , and this is also valid for the uni-directional HV MOS device. When drain-source voltage (Vds) is applied to the HV MOS device, a depletion region grows in the n- offset. The effect of the electric field from the gate electrode on the depletion region causes the drain-side channel terminal voltage to saturate at a low voltage. This reduces the voltage across the channel, and hence increases the breakdown voltage between the drain and source. Moreover, as the drain-side channel terminal voltage saturates in the triode region, gm is reduced.

 

3. Application of Bi-directional HV MOS Model to Uni-directional HV MOS Device

In this section, I directly apply the bi-directional HV MOS model and its parameter extraction technique to the uni-directional HV MOS device, and investigate the results. The bi-directional HV MOS model parameter extraction technique is outlined below [4] - [5]:

  1. First, extract all BSIM3v3 parameters by the standard method.

  2. Then set the value of VSAT to a large value (e.g., 1x109 m/sec) assuming a long-channel device.

  3. Optimize AGS and DELTA at the same time. This is to optimize the saturation voltage of the drain-side channel terminal Vdsat and the source resistance due to the offset region.

Using the above procedure for the bi-directional HV MOS device, the parameter AGS optimizes Vdsat and source resistance in a well-balanced manner, and the measured and simulated I-V characteristics match well. Furthermore, this method can precisely reproduce the gm-reduction phenomenon, which is inherent to HV MOS devices. On the other hand, step II in Table 1 shows the parameters obtained by directly applying the bi-directional HV MOS device model and parameter extraction technique to the uni-directional HV MOS device, and Figure 2 shows a comparison of the measured and simulated I-V characteristics. In Figure 2 large discrepancies are observed between the measured and simulated I-V characteristics.


Figure 2. Comparison between measured and simulated.
(with the bi-directional HV MOS model)
I-V characteristics of the 45V HV MOS device.

 

4. Proposed Uni-directional HV MOS Device Modeling Technique

In this section I propose a uni-directional HV MOS modeling technique: I use the bi-directional HV MOS model in [4] - [5] as a basis, and the main equations are as follows:

 

Here, W is the channel width, ?eff is the effective mobility, ox is the permitivity of the silicon-oxide film, Vth is the threshold voltage, AGS is the gate bias coefficient of the Abulk, Vdsat is the saturation value of the drain-side channel terminal, Vdseff is the effective drain-source voltage and DELTA is the effective drain voltage smoothing parameter of Vdseff. Where, V?ds is the drain-side channel terminal voltage, which is equivalent to the Vdseff of BSIM3v3.

Vrs is voltage drop across the source resistance in the offset region. It cannot be eliminated from equation (1) as Vrs is inherent for the bi-directional HV MOS model with BSIM3v3. Hence, it is necessary to compensate for part of the drain current component by Vrs in equation (1) for the uni-directional HV MOS model. Here, I define the drain current Idrs0 in which the voltage Vrs in equation (1) is eliminated as shown below. Idrs0 is a model equation for the uni-directional HV MOS device model.

Further, by defining Ivrs as the variable component of drain current due to Vrs, I obtain the following expression:

 

The above expression indicates that the way to compensate for Ivrs in the uni-directional HV MOS model is to optimize Idrs0 by making it larger than Ids by the value of Ivrs. Here it can be assumed that the value of Ids is equivalent to the measured data. Suppose the parameter AGS is set to a large negative value, the value of Abulk in equation (4) increases, which in turn decreases the value of Vdsat in equation (5) and results in decreasing the value of Idrs0. At the same time, Abulk increases the value of Ivrs larger. So, AGS cannot optimize Vdsat correctly, and Ids cannot represent the gm-reduction (refer to section 7.). In addition, the value of Ivrs cannot be obtained directly by calculation; instead use the following equation:

I propose the following model which can express the gm-reduction.

  1. BSIM3v3 SPICE model combines the source and drain resistance with Rds (whose value depends on Vgs) as follows:




    where RDSW is the source and drain resistance per unit channel width and PRWG is a Vgs coefficient. Rds is incorporated in the drain current expression of the simplified model as an explicit function of Gds0 shown in equation (3), and Rds hardly affects the saturation voltage (Vdsat) of BSIM3v3. Note that Gds0 has Rds in its denominator, and by making Rds a function of Vgs, it is possible to accurately express the gm-reduction for Idsr0 and Ids mathematically.


  2. Rds provides the gm-reduction for Idrs0 and Ids, but they are not the same. Idrs0 with a larger absolute value has larger gm-reduction, so that it can give most appropriate gm-reduction in order to compensate the value of Ivrs, which is Idrs0 - Ids.

  3. Rds has little influence on Vdsat, and it can be utilized independently of AGS.

  4. AGS can be used to optimize the absolute value of Ids, through Vdsat.

  5. For HV MOS devices, both Vgs-caused mobility degradation effect and gm-reduction occur at the same time and influence of the latter is more predominant. So in the HV MOS model, it is possible to ignore the mobility degradation effect. By defining ?eff as a constant regarding to Vgs, we can obtain about five times faster optimization of the parameters for the parameter extraction tool.

 

5. Proposed Parameter Extraction Technique for Uni-Directional HV MOS Device Modeling

In this section I describe the proposed parameter extraction technique for the uni-directional HV MOS model which can be implemented by using a SPICE model parameter extraction system, such as UTMOST [6].

  1. First, extract all BSIM3v3 parameters by the standard method (step I in Table 1).

  2. Then set the value of VSAT to a large value (e.g., 1x10) assuming the long channel model.

  3. Optimize the parameters of U0, RDSW, PRWG, AGS, and DELTA together in all the triode region (up to close to the saturation region) i.e., from (Vds=0V, Vgs=1.93V) to (Vds=20V, Vgs=45V). RDSW and PRWG have to be optimized such that Rds expresses gm-reduction of Idrs0 while AGS has to be optimized such that Abulk and Vdsat compensate for Ivrs.

  4. Optimize PDIBLC1 and PDIBLC2
  AGS U0 UA RDSW PRWG
Step I 0.084 616 0.7x10 3.8x10 0.0
Step II -0.049 520 0.4x10 3.8x10 0.0
Step III -0.076 463 0.0 1.9x10 0.092
Step IV -0.077 588 0.0 5.5x10 0.018

Table 1. Extracted BSIM3v3 Parameter Values for each step.

 

Since optimization of the absolute value of Ids and gm interact with each other, it is necessary to optimize them simultaneously. Step III in Table 1 shows extracted parameter values based on the above procedure, and Figure 3 shows a comparison between the measured and simulated I-V characteristics. I see that good agreement is obtained between the measured and simulated results (except for the region where negative gds appears.).

In Figure 3, accuracy of simulation decreases in the linear region with higher value of Vgs. This is because Rds provides the gm-reduction in all the region. However, gm-reduction due to the drain-side offset region appears only in the saturation region. To compensate for the worsening accuracy, it is effective to implement Step III again by setting the channel length modulation parameter PCLM=0 (or optimize). The 0 value of PCLM amplifies the gm-reduction in the saturation region, so that Vgs dependence of Rds is optimized smaller (Step IV in table 1). As a result of this, gm-reduction caused by Rds in the linear region gets smaller. Step IV in Table 1 shows the parameters with PCLM=0 and Figure 4 shows the comparison between the measured and simulated I-V characteristics in the triode region. Figure 5 shows Ids-Vgs characteristics in triode region. Note that Ids monotonically increases under the condition of Vgs 40V, however, Ids slightly decreases when Vgs 40V, and this phenomenon is more predominant when Vds = 1V than Vds = 2V. This is due to the decrease of the channel voltage of the drain terminal by the influence of the gate electric field.

 


Figure 3. Comparison between the measured and simulated
(with the uni-directional model) I-V characteristics
of the 45V n-channel HV MOS device.

 


Figure 4. Comparison between the measured and simulated
(with the uni-directional HV MOS model and PCLM=0)
I-V characteristics in the triode region.

 


Figure 5. Comparison between the measured and simulated
(with the uni-directional HV MOS model)
Ids-Vgs characteristics in triode region.

 

References

  1. Y. Cheng, M.-C. Jeng, Z. Liu, J. Hubg, M. Chen, P. K. Ko and C. Hu, "A Physical and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation, " IEEE Electron Devices, vol.44, no.2, pp.277-284 (Feb. 1997).
  2. J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, M. Chan, P. K. Ko and C. Hu, BSIM3 Manual (version 2.0), University of California, Berkeley, (1994).
  3. BSIM3v3 Manual (final version), University of California, Berkeley,(1995).
  4. T. Myono, S. Kikuchi, K. Iwatsu, E. Nishibe, T. Suzuki, Y. Sasaki, K. Itoh and H. Kobayashi, "High-Voltage MOS Device Modeling with BSIM3v3 SPICE Model, "IEICE TRANS. ELECTRON, vol.E82-C, No.4, pp630-637, (April 1999).
  5. T. Myono, E. Nishibe, S. Kikuchi, K. Iwatsu, T. Suzuki, Y. Sasaki, K. Itoh and H. Kobayashi, " Modeling and Parameter Extraction Technique for High-Voltage MOS Device", Proc. of International Symposium on Circuits and Systems, pp.230-233, Orlando Florida (June 1999).
  6. UTMOST III Extraction Manual,Vol.1, ver. 12.03, SILVACO International, Santa Clara, CA