MOS31 JFET/MOSFET Model Now Available in SmartSpice

Introduction

Silvaco now offers the MOS31 JFET/MOSFET model originally developed by Philips [1] as part of the SmartLib product-independent model library. This model is available within SmartSpice as level 31.

The MOS31 JFET/MOSFET model is an integral part of a high voltage MOS macro-model. This long channel JFET/MOSFET model has been especially developed to describe the lightly doped drift region of LDMOS, EPMOS and VDMOS devices. Both vertical and lateral versions of DMOS exist. The vertical device has the greater current-carrying capability and is mainly used as a discrete device in high-power applications. The lateral type serves as an output driver in high-voltage and power ICs.

 

Physical Effects

The main effects modeled in this MOS31 model are described below :

  • Accumulation at the surface (MOSFET)
  • Depletion from the surface
  • Depletion from the bulk
  • Pinch off mode
  • Velocity saturation in the channel
  • Gate charge model
  • Substrate charge model
  • Noise model

 

Simulation Model

The MOS31 model has only 14 physical parameters (RON, RSAT, VSAT, PSAT, VP, TOX, DCH, DSUB, VSUB, VGAP, CGATE, CSUB, TAUSC, ACH), 2 flicker noise parameters (KF, AF). The SI units are used and the new Philips velocity saturation model has been implemented by default. The gate oxide thickness TOX leads to choose between a MOSFET device (TOX>0) or a device without depletion at the surface (TOX<0).

 

DC Static Model

The model parameter VERSION has been implemented in order to choose the Philips velocity saturation model. By default, VERSION=30.2. The old Philips models is still available (VERSION=30.0). The dc characteristics are plotted on Figure 1 for both calculation method (ids -vds) and on Figure 2 (ids - vgs). The drain current still increases with drain voltage due to the velocity saturated current flow.

Figure 1. MOS31 dc simulation with version=30.0
(@mn1[cd]) and version=30.2 (@mn2[cd]).

 

 

Figure 2. DMOS dc simulation. @dmos[cd] versus vgs.

 

 

The electrical circuit of DMOS model consists of a low voltage MOS9 in series with one MOS-FET device MOS31. An example of its characteristics is plotted on Figure 3 for direct and reverse biases. In agreement with the technology, the results are dissymmetrical.

Figure 3, DMOS dc simulatioln. @dmos_inv[cd] versus vds for
reverse bias and @dmos_dir[cd] versus vds for direct bias.

 

 

Noise Model

SmartSpice Common Equations for the 1/f and the shot noise are available using NLEV flag.

 

Ouput Device Variables

Usual device output variables for MOS31 model like node currents, conductances, various charges and capacitances can be printed, stored and/or measured.

 

References

  1. A complete description of the model can be found at the following internet address: http://www-us.semiconductors.philips.com/Philips_Models/
  2. SmartSpice/UTMOST III Modeling Manual Volume 1 (Silvaco International)

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