Mixed Circuit Device Simulation of Single Event Upset in a Memory Cell


Introduction

This article presents Single Event Upset (SEU) simulation of a SRAM cell using MixedMode3D. MixedMode3D provides the capability to simultaneously perform circuit simulation coupled with three-dimensional device simulation. This allows one to examine the internal operation of a three-dimensional numerically simulated device and predict the response of the attached circuit in a self consistent manner.

When an ionized particle interacts with a semiconductor, electron-hole pairs are generated along the path of the incident particle [1]. These generated electron-hole pairs can be transported through the semiconductor by drift and diffusion processes, which ultimately can affect transient device currents. Under certain biasing conditions the transient currents can alter the previously stored state of the circuit, causing an error in the data stored in the circuit. This phenomenon is generally referred to as Single Event Upset (SEU) [2].




Simulation Results

Inputs to MixedMode3D are defined in a text file and include the following information: netlist representation of the circuit, model specifications for the numerically simulated device, SPICE model specifications and parameters, SEU strike definition, and biasing conditions for DC and transient analysis.

A schematic diagram of a six transistor SRAM cell is shown in Figure 1. Five of the six devices shown are simulated with appropriate SPICE models to describe their electrical characteristics. The sixth transistor (AN1) is a three-dimensional numerically simulated NMOSFET. The electrical characteristics of device AN1 are simulated by solving Poisson's equation and current continuity equations at discrete 3D grid points.



Figure 1. Schematic Diagram of a Six Transistor SRAM Cell



Using DevEdit3D a three-dimensional NMOSFET (Figure 2) is created by defining the material regions, doping concentrations, and electrodes. After building a 3D mesh for the NMOSFET, the information is stored as a structure file for use in the MixedMode3D simulation.





Figure 2. Three-Dimensional NMOSFET Structure
Created With DevEdit3D.



The DC biasing of the SRAM circuit sets the word line (node six) to zero volts, and nodes three (drain of AN1) and two, to three and zero volts, respectively. This biasing scheme sets the initial condition of the circuit for subsequent transient analysis.

The description of the SEU strike is specified on the SINGLEEVENTUPSET statement. Entry and exit locations of the SEU particle are defined using (x,y,z) coordinates for each point. The single event upset track is assumed to be cylindrically shaped with the cylinder's center located along the line defined by the entry and exit locations. Electron-hole pair generation rates along the SEU track can be specified as a function of the radius of the cylinder, the length of the track, and the duration of the charge generation pulse [3]. Figure 3 shows the normalized charge generation pulse used in the simulation. The maximum charge occurs at 8 picoseconds and decreases in a Gaussian fashion. Figure 4 shows the electron concentration distribution in the device resulting from a SEU strike directed from the upper left-hand corner to the lower right-hand corner.





Figure 3. Single Event Upset Normalized
Charge Generation Versus Time.





Figure 4. Three-Dimensional NMOSFET Structure
Showing Location of Single Event Upset Strike.



Transient analysis is carried out for ten nanoseconds with an initial time step of ten femtoseconds. Figure 5 shows the resulting node voltages during the transient analysis. The initial voltage on the drain of AN1 (node three) is three volts. As the SEU strike enters the NMOSFET, electron-hole pairs are created and the voltage at the drain of AN1 (node three) is reduced to approximately zero volts. This low voltage state on node three causes transistor MP2 to begin conducting, and the voltage at the drain of MP2 (node two) begins to increase. When the external source of electron-hole pairs is removed, the system recovers and the initial potential values are restored at nodes two and three. If the duration of the strike had been longer, a complete reversal in the state of nodes 2 and 3 would occur.




Figure 5. Internal SRAM storage Node
Voltage Versus Time.


Figure 6 shows isosurfaces of electron concentration in the three-dimensional NMOSFET at two times during the transient analysis. Figure 6(a) shows the electron concentration before the SEU event. Figure 6(b) shows electron concentration isosurfaces when the electron-hole pair generation from the SEU strike is near a maximum (approximately 8 picoseconds). The corresponding potential distributions for these two cases are shown in Figure 7.



Figure 6. Electron Concentration Isosurfaces (a) Before SEU Strike (b) During SEU Strike When Electron-Hole Pair Generation is Near a Maximum
Figure 7. Potential Isosurfaces (a) Before SEU Strike (b) During SEU Strike When Electron-Hole Pair Generation is Near a Maximum.

Summary

Simulation of Single Event Upset of an SRAM cell with MixedMode3D was presented. Predicting circuit responses due to ionized particle interactions with semiconductor devices and visualizing the internal operation of a three-dimensional device under these conditions are valuable tools for device design and circuit testing.

References

[1] IEEE Nuclear and Space Radiation Effects Conference Short Course
      Chapter 3, Snowbird, Utah, July, 19, 1993. 

[2] G. C. Messenger and Milton S. Ash
      "The Effects of Radiation on Electronic Systems"
      Chapter 8, Van Nostrand Reinhold, New York, NY, 1992.

[3] ATLAS Users Manual