Scholar

 

An Advanced Hierarchical Schematic Capture

Introduction

The debut of Silvaco's new schematic editor, Scholar, is drawing closer. Scholar is a sophisticated design tool which derives its power and flexibility from the fact that it is built on top of the general purpose circuit database. Scholar has both a fully functional command language, and an easy to use graphical front end. As it has been developed in-house, it will provide unprecedented interoperability with Silvaco's flagship SPICE simulator, SmartSpice. The planned addition of an EDIF interface will provide complete compatibility with existing circuit libraries.

 

Underlying Structure

Scholar is built on top of Silvaco's in-house wirelist database library. The wirelist has been designed to be a superset of a SPICE netlist, extending the concept to include everything from straight forward analog simulation to parasitic extraction. It forms the backbone for Silvaco's forthcoming EDA tools, enhancing interoperability and enabling an unprecedented level of integration.

Scholar is comprised of several functional blocks. A comprehensive netlisting module converts wirelists, stored in the wirelist database, into hierarchical or flat netlists. The interpreter module uses a fully featured programming language tailored for use with the schematic editor to provide customization and a command line interface to most of Scholar's functionality.

 

Current Development

The low-level libraries which underpin Scholar's command-line functionality are virtually complete. Work is now progressing on implementing the graphical user interface. A complete set of basic schematic editing features are already implemented, along with a library of standard components. Completed designs can be verified with a design rule checker which automatically detects common problems such as short or open nets or dangling wires. Figure 1 shows the current Scholar front-end, along with a diagnostic error caught by the rule checker.

Figure 1. Schematic & Rules checker.

 

Work is also in progress on fine-tuning the interface between Scholar and SmartSpice. SmartSpice analysis options and include files are supported through Scholar menus, and Scholar will run SmartSpice automatically when all required control cards have been generated.

 

Future Direction

The next milestone for Scholar is the provision of comprehensive back annotation and cross-probing features. Back annotation allows the results of a simulation to be displayed directly in the schematic window. Cross-probing gives the user an easy way to query circuit parameters and output waveforms by selecting wires and components directly on the schematic. Further tightening of the interface to SmartSpice will bring even more parameters under the control of Scholar.

The foundations of Scholar's design management layer are in place, supporting design locking and versioning. The finishing touches will futher improve functionality, providing a fully automated environment for maintaining multiple branches on a design tree.

 

Conclusion

The imminent release of Scholar will provide Silvaco's customers with a complete schematic design and simulation solution. The tight integration with SmartSpice and other tools enabled by the common database, in conjuction with the support of an industry-standard EDIF interface, make Scholar an extremely useful new tool in Silvaco's product line.