Calibrating Reverse Short Channel Effects in MOSFETs

 

Introduction

This article focuses on the effects of process and modeling parameters on device electrical characteristics and uses the threshold voltage versus gate length of a n-MOSFET as an illustration. It has long been the adage of experienced TCAD users that the correct modeling of the process flow should represent approximately 90% of the effort, the remaining effort being directed towards electrical device modeling. In other words, if the process flow is correctly modeled, the basic electrical characteristics will be largely correct. This truism is based on the fact that device physics is well understood and most values required for device modeling are well known for silicon. These device modeling parameters are included as the default values in ATLAS.

 

Modeling Short Channel Effects

The Short Channel Effect (SCE) and Reverse Short Channel Effect (RSCE) are strongly affected by changes in the process flow and are caused primarily by implant induced defect enhanced diffusion. These effects therefore present themselves as ideal candidates for tuning implant damage models in ATHENA.

The short channel effect is universal in MOSFETs and represents the gradual shorting together of the source and drain diffusions as the gate length reduces to low values. This one effect allows calibration of two phenomenon, namely the lateral spread of the as-implanted source-drain dopant profiles, and the effects of subsequent diffusion steps.

The reverse short channel effect only occurs when the peak of the channel implant, usually boron, lies below the silicon-SiO2 interface in the centre of a long channel MOSFET. Enhanced diffusion, caused by lateral implant damage to the source-drain area, moves the peak concentration of boron closer to the surface in these regions. For short channel MOSFETs, therefore, a higher percentage of the channel has a higher concentration of boron at the surface than for long channel devices. Short channel devices therefore have a higher threshold voltage than long channel devices until the channel becomes so short that the usual short channel effect takes over. The reverse short channel effect therefore allows the calibration of defect production and annealing effects in both the bulk of the silicon and at the gate oxide interface where the interface acts as a sink for defects. Appropriate models for these physical effects should be enabled in ATHENA before the source/drain implantation:

METHOD FULL.CPL CLUSTER.DAM HIGH.CONC

 

Parameter Tuning

ATHENA allows user definable damage and anneal factors for accurate tailoring of process models resulting in good predictability for the final device. For a given channel implant dose and energy, the magnitude of the peak value of reverse short channel threshold voltage will be strongly related to the magnitude of the initial implant damage. The implant damage factor can be adjusted by specifying the CLUST.FACT parameter. The effect of adjusting the CLUST.FACT parameter for an otherwise fixed typical process flow, is shown in Figure 1. Initial experiments have suggested a value of 1.4 to be approximately correct.

Figure 1. Showing the effect of changing the CLUST.FACT damage factor in ATHENA.

 

 

The important role of damage in determining threshold voltage is clearly demonstrated in Figure 1. The importance of correctly modeling the damage in ATHENA is also indicated, since the large range in the results was obtained by changing just the implant damage factor CLUST.FACT in ATHENA. If the process flow has been accurately modeled, calibrating the correct damage factor to a particular process is merely a question of matching the correct magnitude of change in the peak threshold voltage. Thus, one parameter has now been calibrated.

The correct rate of interstitial dissipation at the silicon-gate oxide interface can also be calibrated using this plot. The rate of roll-off of threshold voltage with increasing gate length is a result of how far interstitials generated during the source-drain implants can diffuse before being dissipated at the surface. The tuning parameter associated with surface interstitial dissipation is KSURF.0. A higher value of KSURF.0 will give rise to a greater roll-off in threshold voltage with gate length. This parameter can also therefore be unambiguously calibrated to a particular process.

Finally, the rate of roll off for very short gate lengths is a result of how much lateral dopant spread occurred during implantation and subsequent diffusion. Since the annealing steps in the process are known, the only variable to tune is the implant lateral spread parameter. This parameter is called LAT.RATIO1 in ATHENA.

To conclude this brief summary on tuning ATHENA for MOSFETs, it has been shown that using just one set of measured data, namely a plot of threshold voltage variation with gate length, three of the most important parameters in ATHENA can be unambiguously tuned to their correct values. To confirm calibration of the process simulation, the user should perform additional device simulations and compare these results to measured data not used in process calibration. Typically, this could be similar data with a substrate bias. It is crucially important that the user has used appropriate models in the process simulation before turning to tuning parameters. This includes the models CLUSTER.DAM, FULL.CPL and HIGH.CONC in the method statement before implantation statements where the dose exceeds approximately 1e13/cm2 and the model TWO.DIM for oxidations and implantations less than 1e13/cm. The FERMI model should only be used where no oxidation or implantation damage has occurred.

 

Process Parameter Effects

This section shows the effects of changing actual process parameters on the electrical results of a typical MOSFET process flow. In this article, the effect of activation anneal temperature has been chosen as a process variable. This particular parameter was chosen because the effect of variations in activation anneal temperature are the opposite of what would be expected intuitively. Specifically the lower the anneal temperature, the greater the dopant diffusion becomes. To understand this phenomenon, accurate modeling of defect diffusion is key. The high rate of dopant diffusion for low temperature anneals is a particular problem for sub-micron radiation hardened devices, where anneals above 850C0 have to be avoided.

Figure 2 shows a set of modeling experiments where the CLUST.FACT parameter has been fixed, while the anneal temperature / time parameters are the variables. The minimum time for a low temperature anneal is limited by the rate of damage removal. There is little point in using a short activation anneal at 850C for example, since the material would still be so damaged that the device electrical characteristics would be very poor.

 

Figure 2. Showing the effect of anneal conditions on the threshold voltage of a MOSFET.

 

For the low temperature anneals, an anneal time as short as possible was chosen, consistent with a significant amount of damage removal; whilst the high temperature anneals are, if anything, longer than required. The modeled effects are therefore understated. Figure 2 shows that for the two highest temperature anneals (1000 and 1050°C), the dopant has almost not moved at all to the extent that the reverse short channel effect (RSCE) is non existent and the short channel effect (SCE) occurs for shorter channel lengths. As the anneal temperature reduces to 850°C, the high dopant diffusion effects such as RSCE and SCE become greatly enhanced.

The understanding of this counter-intuitive result relies on the realization that two competing physical effects occur at the same time during an activation anneal and each effect has a significantly different temperature coefficient. These two effects are:

  • defect enhanced diffusion
  • defect annealing

In effect what happens at the two extremes of anneal temperature is as follows: for low temperature anneals, the defects are almost insoluble and remain in the silicon for very long times. The huge increase in diffusion rate for defected material (approximately x1000) therefore results in the dopant diffusing large distances before the defects are dissolved. For the high temperature anneals, all the defects are dissolved in a very short time, so almost no defect enhanced diffusion occurs. For the remainder of the high temperature anneal, therefore, only intrinsic diffusion takes place which is approximately one thousand times slower. An important result of this is that for high temperature anneals most of the diffusion takes place during the temperature ramp-up phase, even for rapid thermal anneals. It is therefore vitally important to include the temperature ramp-up of the first heat cycle after heavy implants during the process simulation. The ramp down is much less important.

 

Summary for MOS Simulations

Measured data for Vt versus length is an invaluable aid for tuning purposes. Defect damage during implantation and defect combination coefficients can be tuned to this curve. Since diffusion temperature after heavy dose implants is a key variable in determining any SCE or RSCE, it is important to include the ramp-up steps of final diffusion cycles.