ATLAS/MixedMode Simulation of a Three Stage CMOS Ring Oscillator
Part I: MixedMode Setup

Introduction

Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One of the most useful results obtainable from a ring oscillator test structure is the delay time per gate. This information is especially important for successful design of high speed clock circuits, such as Phase Locked Loops (PLL's) and Voltage Controlled Oscillators (VCO's).

This article is aimed at demonstrating the simulation of a three stage CMOS ring oscillator. Using ATLAS/MixedMode, MOSFET devices in the circuit are simulated numerically. For Part I, both NMOS and PMOS devices were created with analytical doping profiles using ATLAS. In Part II these devices will be created from process simulation using ATHENA and process variations will be analyzed. Part II will be published in the next issue of the Simulation Standard.

MixedMode simulation provides the capability to simultaneously solve the device and circuit equations using fully coupled algorithms. This allows circuit simulation including devices for which no compact SPICE model exists. In addition, device creation in ATHENA can yield the optimum process conditions for a given device or the effects of process variations on circuit performance.

 

Mixed Circuit/Device Simulation

The schematic diagram of a three stage CMOS ring oscillator is shown in Figure 1. Each NMOS device in the circuit is defined in ATLAS using the REGION, ELECTRODE, and DOPING statements (Figure 2), resulting in the structure shown in Figure 3. PMOS devices are defined in a similar manner, but with opposite doping polarity. These virtual devices along with the load capacitors (C1=C2=3fF and C3=6fF) are used to define the ring oscillator circuit in MixedMode. The syntax used is included in Figure 6, where the device name, node designation, corresponding structure file, and width are specified for each device.

Figure 1. Schematic Diagram of Three Stage CMOS Ring Oscillator Used in MixedMode Simulation.

 


# Regions region num=1 y.min=0 silicon region num=2 y.max=0 oxide # Electrodes elec num=1 x.min=1 length=1.0 name=gate elec num=2 left length=1.0 y.min=0 y.max=0 name=source elec num=3 right length=1.0 y.min=0 y.max=0 name=drain elec num=4 substrate name=substrate # Doping profiles doping uniform conc=1e16 p.type doping gauss conc=1e17 p.type char=0.2 peak=0.15 doping gauss conc=1e20 n.type junc=0.17 x.right=1.0 ratio=0.7 doping gauss conc=1e20 n.type junc=0.17 x.left=2.0 ratio=0.7

Figure 2. ATLAS Statements Used to Define the NMOS Device for MixedMode Simulation.

 

Figure 3. Cross Section of NMOS Device Created in
ATLAS and Used in MixedMode Simulation.

 

Simulation commences by applying a piecewise linear waveform (0 to 5 volts) with a rise time of 50 picoseconds to the supply voltage (V2 in Figure 1). Transient analysis of the circuit is carried out for 800 picoseconds, providing a few periods of oscillation. The voltages versus time at nodes one, three, and four are plotted in Figure 4. The onset of oscillation is readily seen between zero and approximately 300 picoseconds, where the peak to peak magnitude of V[1], V[3], and V[4] increases until reaching a maximum after 300 picoseconds.

Figure 4. Three Stage CMOS Ring Oscillator Node Voltages Versus Time.

 

From the time variation of voltage at node one, the delay time for each gate can be determined from the following equation [1,2]

(1)

where T is the period of oscillation, and n is the number of gates in the ring oscillator circuit. From Figure 4, the period is estimated to be approximately 315 picoseconds, and thus the delay per gate using Equation 1 is determined to be approximately 52.5 picoseconds.

Switching operation of one inverter stage is shown in Figure 5, where drain currents are displayed in the top half, and node voltages V[3] and V[4] are displayed in the bottom half. When V[3] is at a maximum or minimum value, the corresponding drain currents are very small. As V[3] transitions from the maximum or minimum values, the drain currents begin to increase toward their maximums.

 

Figure 5. Switching Operation of One CMOS Inverter Stage.
Drain Currents (top) and Node Voltages (bottom).

 

aM1 3=drain 1=gate 0=source 0=substrate infile=nmos.str width=5.
aM2 3=drain 1=gate 2=source 2=substrate infile=pmos.str width=15.
c1 3 0 3ff
vdd 2 0 0
aM3 4=drain 3=gate 0=source 0=substrate infile=nmos.str width=5.
aM4 4=drain 3=gate 2=source 2=substrate infile=pmos.str width=15.
c2 4 0 3ff
aM5 1=drain 4=gate 0=source 0=substrate infile=nmos.str width=5.
aM6 1=drain 4=gate 2=source 2=substrate infile=pmos.str width=15.

Figure 6: Statements Used in MixedMode Simulation to Define Three Stage CMOS Ring Oscillator Circuit

 

Summary

The simulation of a three stage ring oscillator in ATLAS/MixedMode has been demonstrated. Definition of the individual MOSFET devices was accomplished using analytical doping profiles in ATLAS. Examining process variations using ATHENA will be investigated in Part II. Part II will be published in the next issue of the Simulation Standard. Example syntax of device definition and specification in the ring oscillator circuit was included. The gate delay was extracted from the transient analysis output voltage versus time.

 

References

[1] T. Ohzone, T. Miyakawa, T. Matsuda, T. Yabu, and S. Odanaka,
"Performance Evaluation of CMOS Ring-Oscillators with Source/Drain Regions Fabricated by Asymmetric/Symmetric Ion-Implantation,"
Proc. IEEE 1997 International Conference on Microelectronic Test Structures, Monterey, California, pp. 131-136, March 1997.

[2]. A. Mahajan, G. Cueva, M. Arafa, P. Fay, and I. Adesida,
"Fabrication and Characterization of an InAlAs/InGaAs/InP Ring Oscillator Using Integrated Enhancement and Depletion Mode High-Electron Mobility Transistors, "
IEEE Electron Device Letters, Volume 18, Number 8, pp 391-393, 1998.