SmartSpice v.1.5.5 Release Notes

1 Models

1.1 BSIM3 Version 3.2 (Level=8) Model

1.1.1 Silvaco Model Implementation
The latest Berkeley BSIM3v3.2 model of June 16 1998 has been integrated into SmartSpice 1.5.5. The Silvaco implementation of the Berkeley BSIM3v3.2 model can be invoked by specifying the model selector LEVEL=8 and the version selector VERSION=3.2 in the .MODEL definition. This version is now used as the default BSIM3v3 model. Older BSIM3v3 models can be invoked by specifying VERSION=3.0 or VERSION=3.1.

1.2 BSIM3 Version 3 (Level=8) NQSMOD Model

A new improved Non-Quasi Static capacitance model was implemented in the BSIM3 v3.0, v3.1, and v3.2 Level=8 models. This model can be invoked by specifying the model or device selector NQSMOD=5. It is supported in the .TRAN and .AC analyses. The original Berkeley NQSMOD=1 model is also supported. To model MOSFET devices the NQSMOD=5 model is recommended rather than the NQSMOD=1 model.

1.3 BSIM3 Version 3 (Level=8) Noise Model

The SmartSpice common MOSFET noise model equations have been corrected in the BSIM3 Version 3.0/3.1/3.2 (Level=8) model. The model invoked by the selector NLEV is now consistent with the SmartSpice Modeling Manual.

1.4 BSIM3 Version 3.2 (Level=81) Model

The original Berkeley BSIM3v3.2 model implementation can be invoked by specifying the model selector LEVEL=81 in the .MODEL definition. This VERSION=3.2 is now used as the default BSIM3v3 model. Older BSIM3v3 models can be invoked by specifying VERSION=3.0 or VERSION=3.1. All .MODEL definitions in the input deck must specify the same BSIM3v3 model version. The BSIM3v3 v3.0, v3.1 and v3.2 models cannot be invoked simultaneously during the same run. The BSIM3v3.2 LEVEL=81 model implementation uses the original Berkeley BSIM3v3.2 source code. There is only one change: it allows output of charge and intrinsic capacitance values.

1.5 HVMOS (Level=88) Model

SmartSpice now supports a new BSIM3v3.2 based Level=88 MOSFET model. developed for high-voltage and analog applications.

 

The following physical effect are taken into account in this model:

  • Forward and Reverse Modes of Operation
  • Asymmetry of All Parasitics (Diodes and Resistances)
  • Bias Dependence of External Resistances
  • Dependence of Mobility Degradation on Vds
  • Bias Dependence of VSAT
  • Transconductance Gm Reduction in Saturation at High Vgs
  • Physics based NQSMOD capacitance model

 

1.6 BSIM3SOI (Level=25) Model

The Berkeley BSIM3SOI v1.2 model released in December 1997 is now available within SmartSpice as MOSFET level=25 model.

The original Berkeley model implementation can be invoked by specifying the selector Berk=2. The Silvaco model implementation is invoked by specifying Berk=-2.

The older Silvaco model implementation of October 1997 is also supported under the selector Berk=-1.

All implementations produce virtually identical results when commonly acceptable model parameter sets are used. However, the Silvaco Berk=-2 implementation supports a number of additional parameters and options, and provides certain improvements compared to what is supported in the Berk=2 (Berkeley) and Berk =-1 ( older Silvaco) Level=25 models.

 

1.6.1 Impact Ionization Current
In the Berkeley SOI model implementation, the impact ionization current Isub depends on the model parameters ALPHA0 and BETA0. The current Isub represents a current directed from the drain to the bulk.

The simulation results produced by the device simulator ATLAS show that the partitioning of the impact ionization current between bulk and source significantly depends on the channel lengths.

In long channel devices 100% of the impact ionization current flow into the bulk. in short channel devices the entire impact ionization current flows into the source.

In the Silvaco Berk=-2 model implementation the impact ionization current directed from the drain to the source can also be modeled using the PSCBE2 and PSCBE1 parameters.

 

1.6.2 Intrinsic Capacitance Model CAPMOD=0
The Berkeley SOI model implementation supports the intrinsic capacitance models CAPMOD=2 and 3. The Silvaco Berk=-2 model implementation also supports the CAPMOD=0 intrinsic capacitance model. It provides the best convergence and performance. The most complicated model is CAPMOD=3. This Berkeley model has the worst convergence and performance. The Berkeley CAPMOD=2 capacitance model has better convergence and performance than the CAPMOD=3 model, but much worse than the CAPMOD=0 model.

The Vfbcv model selector can be used with the CAPMOD=0. The recommended value is INTCAP=1. In this case, the flat band voltage is calculated in the same manner as for CAPMOD=2. The INTCAP selector will be ignored if the VFBCV parameter is explicitly specified in the model card.


1.6.3 Binning Parameters
A number of binning parameters were reimplemented in the Level=25 Berk=-2 model. The binning procedure is supported for the following model parameters:

VHT0, RDSW, U0, KETA, K2, UA, PSCBE1, and PSCBE2.

It is identical to that in the BSIM3 v3.1 MOSFET Level=8 model.

1.6.4 Geometry Parameter Calculation
In the Berkeley implementation, the geometry parameters NRD, NRS, AD, PD, AS, and PS can only be specified as device parameters.

In the Silvaco Berk=-2 model implementation, the geometry parameters NRD, NRS, AD, PD, AS, and PS can also be calculated as functions of Weff and the model parameters shown in Table 1.

 

 

 Parameter

 Default

  Units

 Description
  LD

  0.0

 m

 Length difference.
 LDIF

  0.0

 m

 Lateral diffusion.
 HDIF

  0.0

 m

 Heavy doped region length.
 RS

  0.0

 Ohm

 Source resistance.
 RD

  0.0

 Ohm

 Drain resistance.
 RSC

  0.0

 Ohm

 Contact source resistance.
 RDC

  0.0

 Ohm

 Contact drain resistance.
Table 1. Model Geometry Parameters.

 

 

1.7 BJT Model

The temperature parameters TRC and TRB have the same effect as the parameters TRC1 and TRB1 respectively.

The option CAPDC (DCCAP) is now applied to the BJT model.

The following BJT device output parameters are now accessible for direct post-processing under the option CAPDC are shown in Table 2.

 

 

 Parameter  Description
 Capbe or Cpi Base-emitter junction internal capacitance.
 Capbc or Cmu Base-emitter junction internal capacitance.
 Capsub Substrate junction capacitance.
 Capbx Base-collector external capacitance.
 Ft is now calculated as a function of junction capacitances.

Table 2. BJT Device Output Parameters

 

 

Example

.PRINT DC @q1[Capbe] @q1[Capbc]

.PRINT DC @q1[Cpi] @q1[Cmu]

Note: In older SmartSpice versions, the statement .PRINT DC @q1[Cpi] @q1[Cmu] prints capacitance currents rather than capacitances. In SmartSpice the option JCAP determines the actual capacitance equations used in the Diode and BJT models. The default JCAP=0 selector activates the model parameter FC (default FC=0.5) for Vd > 0. The selector JCAP=1 activates a simplified capacitance equation with FC=0.

1.8 PTFT (Level 16) Model
The default VTO value is now VTO=-4.5 for the P-channel PTFT Level 16 model. In older SmartSpice releases the same default value of +4.5 is used for both P and N-channel models.

1.9 EKV (Level = 44) MOSFET Model
SmartSpice
now supports the EPFL - EKV (Enz-Krummenacher-Vittoz) MOSFET model. The current version supported in 2.6. All standard analyses are currently supported (i.e., DC, AC, transient, and noise). This model is accessable as a standard MOSFET model, using the level = 44 model parameter.

1.10 Default Model Names
Some devices do not require the user to specify a model in the input deck (i.e., resistor capacitor and inductor). Internally a default model is created to handle these devices. The names used for these internal default models have been changed to prevent conflicts with user-defined models. For instance, the default model used for capacitors is now __Cdefault.

1.11: Version 4.5 of University of Florida (Level = 21) Released
The University of Florida SOI model has been updated to the latest version of the code, Version 4.5.

1.12: TSMC (Level = 18) MOSFET Model
Six new parameters have been added to this model. These parameters model the length, width and area dependence of the source and drain resistance. The parameters are lrs, wrs, prs, and lrd, wrd, prd.

1.13 Common Model Names
In prior versions of SmartSpice, each model name had to be unique, regardless of the type of the model. For example a resistor and a MOSFET model could not share the same name. SmartSpice now allows models of different device types to have the same model name. When a device requiring a model is parsed, the search for the particular model will only return a model of the appropriate type. For example in the following netlist fragment, the model name "n" is used twice, but SmartSpice, will accept both model definitions since they refer to different device types.

.model n r

.model n nmos level=3

r1 1 0 n

m1 1 2 3 4 n l=1u w=1u

 

2 Device

2.1: Behavioral A-device

New parameters were implemented in A-device. These parameters are SCALE, TC1 and TC2. The parameters are used to calculate the multiplier SCALEeff of the A-device output variable (current or voltage) as follows:

SCALEeff = SCALE*(1 + TC1*(TEMP-TNOM) +TC2* (TEMP-TNOM)^2)

The default values are: SCALE=1.0, TC1=0.0 and TC2=0.0.

Example

AR2 5 0 i=v(3) SCALE=2

AC1 3 0 i=v(vcap)*DER.v(3) SCALE=2

ACAP vcap 0 V=V(3) SCALE=5 TABLE(0v 100pF

1v 100pf 5v 1000pf 10v 1000pf)

G7 7 0 PWL(1) 3 0 (0,0 10,-10)

SCALE=7 TC1=0.0 TC2=0.0

E9 999 0 PWL(1) 3 0 (0,0 10,-10)

SCALE=7 TC1=0.0 TC2=0.0

* Bad Syntax * G1 7 0 PWL(1) 3 0

0,0 10,-10 SCALE=1

* Bad Syntax * G7 7 0 PWL(1) 3 0

0,0 10,-10 SCALE=7 TC1=0.0 TC2=0.0

* Bad Syntax * G1 7 0 PWL(1) 3 0

SCALE=1 0,0 10,-10

* Bad Syntax * G7 7 0 PWL(1) 3 0

SCALE=7 TC1=0.0 TC2=0.0 0,0 10,-10

* Bad Syntax * G7 7 0 PWL(1) 3 0

SCALE=7 TC1=0.0 TC2=0.0 (0,0 10,-10)

 

3 Statements

3.1 Parametric Expressions

3.1.1 Parametric Expressions Syntax
Older SmartSpice versions do not recognize certain parameter expressions containing the comma "," and/or "Tab" delimiters. This problem has been corrected.

Example

Older SmartSpice version failed to re-calculate and reload the "gnd," expression in the following pwl specification:

v_mode mode 0 PWL (

+ 0 gnd,

due to the delimiter "Tab" presence in the "gnd," expression.

 

3.1.2 Local Parameter Expressions
If SmartSpice 1.5.5 fails to recalculate a local parameter expression, or to reload a local parameter as a device or model parameter, then smartspice prints warnings rather than terminate the simulation. In this case, the initial device or model parameter value is used.

Example

Warning: ReLoad failed to load parameter

`loth' of type `tree' or `vector'

Warning: Initial parameter value

(=3) is used

Warning: ReLoad failed to load parameter

`vdd' of type `tree' or `vector'

Warning: Initial parameter value

(= 7.5) is used

 

3.2 .GLOBAL Statement

Tab characters can now be used within the.GLOBAL statement to seperate node names.

 

4 Options

4.1 Options ADDK (GENK) and KMIN (KLIM)

SmartSpice now supports the ADDK and KMIN options. The default values are:

ADDK = 0 (OFF),

and

KMIN = 0.01

The options GENK and KLIM have the same effect as ADDK and KMIN respectively.

If the input deck contains inductance packages with the coupling elements K, and the option ADDK=1 is specified, then SmartSpice will generate secondary (hidden) coupling elements.

SmartSpice prints the list of all secondary coupling elements when the option LIST is specified in the input deck.

Secondary (hidden) coupling elements improve stability of the system of equations describing the circuit behavior.

 

4.2 Option DCSTEP

SmartSpice now supports the option DCSTEP. The default value is:

DCSTEP = 0.0 (OFF)

Currently this option is supported for:

1. Linear capacitances.

2. BSIM3 v3.0/3.1 Level=8/49 models.

3. BSIM1 Level=4/13 model.

4. TSMC Level=18/28 model.

If the option DCSTEP=dcstep_val > 0.0 is specified in the input deck, SmartSpice replaces capacitances in the above elements with conductances "cond_val" as follows:

cond_val = cap_val/dcstep_val,

where cap_val is the actual device capacitance value. The capacitances are replaced with conductances during the DC computation phase only. These conductances are released when the circuit is simulated in time domain.

Note: The SmartSpice option DCPATH ( def=1e-11 ) remains active with and without the DCSTEP option. To suppress the DCPATH option specify: DCPATH=0.0.

 

4.3 Option MEASDGT

It allows specification of the number of digits in the output from .MEASURE statements. The default is to use the value of .OPTION NUMDGT. Specifying .OPTION MEASDGT overrides this value, but only for .MEASURE statements.

 

4.4 Option ACCT - Better Component Lists

This option provides a listing of all device models present in the input deck, which appears at the end of the output. In previous releases, particularly for very large decks, the time spent producing the table could be substantial (several minutes). Also, the table categorized devices based on their type (e.g., MOSFET, diode, BJT) rather than on the specific model (e.g., BSIM1, BSIM3SOI, etc.). Therefore if a deck used two different BSIM models, all MOSFETs in the deck would be classified under one entry. This was sometimes misleading, creating the impression that only one model had been used.

With the new table-generation algorithm, performance is not only orders of magnitude faster, it also now lists devices based on their models. This means that decks using two BSIM models will generate two separate entries in the table, eliminating a source of confusion.

Finally, under the old scheme, if the user specified both .OPTION VZERO=2 and .OPTION LARGE, the table could not be generated at all. The new algorithm can generate the table regardless of the other options chosen by the user.

4.4.1 Option CHCKT - Backward Compatibility
While the new table-generation algorithm is now the default, the older algorithm is still available, for compatibility reasons, by specifying `.OPTION CHCKT'. This will probably be removed in a later release.

4.5 Improved System Performance on Solaris2

Aggressive optimization, combined with new algorithms, has significantly reduced the system times reported by some users on certain platforms.

 

5 Post-Processor

5.1 .OP Output in Transient Analysis

.OP output during transisent analysis has been modified to output data at the exact time requested, rather than at the closest actual timepoint to that requested. If the requested time does not coincide with a timepoint, data will be interpolated prior to being output.

In prior versions of SmartSpice some internal node voltages and device operating points were not printed out. This has now been fixed.

 

5.2 Cadence PSF Support

Support for PSF output has been extended to output operating point information for devices. This allows the user to back-annotate the device operating point onto the schematic.

SmartSpice has also been extended to support PSF output for nested AC, DC and transient sweeps.

 

5.3 Hierarchical Device Names

When a device within a subcircuit is flattened, the flattened name is created by appending the device name to the subcircuit path. The first character of the device name is then prepended to the flattened name so that the device type can be identified using only the first character of the flattened name. Hence the flattened name of the device "m1" in the subcircuit "x1" is "m.x1.m1". This name is then used to access device parameters, i.e., id(m.x1.m1) or @m.x1.m1[gds].

In this release it is not necessary to use the preceeding identifier, i.e., "x1.m1" can be used as an alias for "m.x1.m1".