CellRATER from Taveren Technology fast, Accurate Cell Library Characterization for Deep Submicron Timing Flow Improvement

 

John Croix and Jerry Gebhard, Tavern Technology

 

Introduction

Taveren Technology, Inc., a startup company based in Austin, Texas is busy developing the next generation performance characterization tool suite. CellRATER, a cell library characterization tool, is the first product in this suite. It is up to 10 times faster and 10 times more accurate than the competition. This article will attempt to give you an understanding of how CellRATER achieves these goals using Silvaco's SmartSpice, and the benefits that can be gained in the overall timing design flow.

 

Figure 1. Traditional approach to cell characterization.

 

 

Background

Over the past few years, static timing analysis has become an acceptable signoff method for high speed digital designs. Generally, static timing tools fall into 2 categories: cell-based static timers, typically used by ASIC designers, and transistor-based static timers, more commonly used by custom IC designers. Both methods suffer from a lack of accuracy when compared to SmartSpice, but the improvement in analysis time is usually what convinces users the tradeoff is necessary. Both types of timing tools rely on pre-characterized data for the primitive elements in the analysis. Cell-based tools rely on a library of characterization data, typically made up of standard or gate array cells. Transistor-based tools rely on tables of data for various transistor sizes.

The deficiencies of both types of static timers are well known. First and foremost is the fact that they are only as accurate as the characterization data they rely on. Generally speaking, cell-based timers are faster because they deal with less data. One would expect transistor-based static timers to be more accurate due to the finer granularity of the analysis. In practice this isn't always true, and the tradeoffs for this finer granularity are CPU time and limits on the amount of data that can be successfully analyzed. CellRATER was developed in an attempt to give the end user the best of both worlds. Improved accuracy for the cell-based user, and improved throughput for the transistor-based user. (For those users whose tools can run in mixed-mode, cells and transistors at the same time, substituting CellRATER data for standard cells improves the throughput, while maintaining the accuracy)

An additional and equally important benefit to the cell-based user is the positive impact these improved libraries have on synthesis. It is generally accepted knowledge in the industry that problems caused by synthesis are really the fault of poorly developed and characterized libraries.

Traditional Approach

To understand our method of characterization, it is helpful to review the traditional approach. In its most basic form, cell characterization is the process of applying a voltage stimulus to an input pin, placing a capacitive load (Cload) on an output pin, and measuring the propagation delay (td) through the cell and rise/fall times (tout) on the output pin.

Recently this approach was taken a step farther. Attempts to improve the accuracy of cell models led to the development of the non-linear table model. The non-linear table model increases accuracy by allowing the effects of input edge transition time (tin) on the propagation delay (td) and output rise/fall times (tout) to be taken into account. Unfortunately, it still lacks a place-holder for information on variations of Cin with respect to Cload and tin that we can provide. (These variations impact the previous driving stage rise/fall times, and should be included in future versions of the model.)

Typical characterization tools measure the response of a cell at a small number of points that are chosen manually by the user. This limited data set is used to populate the table model, which in turn is used to predict the overall response of the cell. By using interpolation between the points or fitting it to a fixed-form equation, new response values are chosen during static timing analysis or synthesis. Our research has shown that these interpolation errors can typically be on the order of 15-50% of what the true response would be if measured in SmartSpice.


CellRATER's Approach

As contrasted to the above approach, CellRATER can produce a 6x6 lookup table for a combinational or sequential (flip-flop) cell that predicts response to within 0.5% (typical) of SmartSpice, after interpolation by Synopsys. That accuracy is typical across the entire range of response, not just at the measured points. CellRATER uses a unique method of oversampling and data reduction that guarantees more reliable and more accurate results than traditional methods. Yet speed is not compromised. In fact, even though we sample at many more points than other commercially available packages, our runtimes are less. In fact, they can be as much as 10 times less.

 

Data Reduction

Because we collect more data than traditional tools, we have a much better representation of the true response of the cell. However, we are still constrained with producing a "reduced table" of this data (for synthesis and static timing run-time performance reasons). To handle this constraint, we apply innovative error-minimizing techniques to reduce the oversampled data to either a lookup table or set of equation coefficients suitable for use in synthesis, static timing analysis or event-driven simulation tools. For example, if the measured data consisted of 400 points, data reduction could reduce this to 36 points (6x6 table). When this table is used to predict the response of the cell, it would yield typical results within 0.5% of SmartSpice over the entire range of measurement (not just the measured points).

 

Speed

In addition to offering the highest accuracy available, CellRATER offers impressive efficiency. While it might seem that more CPU resources would be required by our oversampling approach, we have demonstrated that by taking advantage of SPICE setup features, it actually takes less time to complete the characterization process.

In addition, for those who have access to multiple, networked computers, the performance of our system scales almost linearly with the number of computers. Our system uses a client-server architecture to take full advantage of your SmartSpice licenses. Because we have a custom interface, the use of SmartSpice as the SPICE engine in our system ensures the most optimum solution for speed.

 

Figure 2. Table model approach to modeling response as a function of Capacitance
Load and Input Transition Time.

 

Ease-of-Use

There is a beneficial side-effect to the oversampling technique. Users do not have to pick their own sampling points. The process is entirely automatic. Ease-of-use doesn't stop there. We supply a set of standard cell templates encoded in our proprietary SpicePILOT language. With our templates, most standard cells can be set up for characterization within a few minutes with little or no changes.

Traditional characterization often involves many steps repeated across hundreds of cells resulting in hundreds, if not thousands, of simulation runs which have to be post-processed, organized, and manually tracked by the user. CellRATER offers a pushbutton system that allows you to manage the entire process reliably for thousands of cells. It tracks SmartSpice jobs seamlessly across any number of distributed computer systems.

Data Management

Another powerful feature of the system is its centralized data storage for both the raw characterization data and the results. An application programming interface (API) allows you to access this data for any purpose ­ reports, cross-checks, regression analysis, charting, etc. This means you don't have to rerun jobs to retrieve the raw data.

External Formats

CellRATER can generate a variety of EDA vendor formats. However, it is easy to generate your own formats by using the data management API to access raw data or results.

Reliability

Characterization is a complex, tedious process involving hundreds or thousands of simulations, potentially across multiple computers. This process must be tracked for consistency and accuracy otherwise errors could be introduced into the flow. For example, a failed simulation job on a given system could prevent a cell from completing normally. With our system, the tedious bookkeeping involved in tracking the characterization of a library is handled automatically and reliably. In the event of an error or job failure due to a power or network outage, our checkpoint feature allows the user to easily restart a characterization from the point of failure.

Other Features

It is important to know the accuracy of your libraries. Without the ability to automatically generate error reports, cell libraries suffer gradual degradation in quality as they progress through design iterations and process changes. With traditional tools, the user must manually pick the new characterization points with each process change or cell design iteration, otherwise additional errors will be introduced into the library data. We pick the characterization points automatically, which means we have accurate data for every change. But as an added benefit, CellRATER includes an integrated analysis module that generates error reports allowing the user to verify the accuracy of the entire library.

As path delays descend into the sub-nanosecond range, the statistical likelihood of input pins switching simultaneously increases. In datapath logic, simultaneous switching is a virtual certainty. Traditional methods ignore the effects of simultaneous switching, introducing inaccuracies of 20% or more into propagation delays, Cin calculations and output rise/fall times. CellRATER offers an optional module that allows the effect of simultaneously switching inputs to be considered.

Benefits to Your Design Flow

Using cell library characterization data built with CellRATER and SmartSpice, cell-based static timing analysis now becomes much more reliable in predicting overall timing performance. Our studies have shown that static timing results on paths of 10-12 levels of logic came within 2% of SPICE for the same circuit. The benefit to you and your design team is timing reports you can believe, the elimination of wasted design time, and higher quality products. Not a bad investment.